Abstract: A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell in a write mode, and electrically separates a bit line pair from the input/output line pair in response to a read column selection signal, a write column selection signal and a first data masking signal. The input/output circuit buffers and provided a signal of the input/output line pair to input/output pins, receives input data from the input/output pins, and buffers the received input data to provide the buffered input data to the input/output line pair. Thus, the semiconductor device can perform a fast data writing operation.

Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

Abstract: In an apparatus and method for automatically correcting a design pattern in view of different process defects, defect characteristic functions that indicate frequencies of each process defect independent from one another are generated, and a normalization factor that indicates relationships between the defect characteristic functions is determined. A general defect characteristic function indicating a frequency of general defects is generated using the defect characteristic functions and the normalization factor. The general defect causes the same process failure as caused by each of the process defects. The design pattern is modified using the general defect characteristic function in such a manner that the frequency of the general defects is minimized when at least one portion of the design pattern corresponding to the model pattern is transcribed on the substrate. Accordingly, the whole design pattern may be automatically corrected based on the general defect characteristic function.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact spacer on internal walls of the contact hole, a first contact plug connected to the contact pad exposed by the contact hole having the contact spacer on the internal walls thereof, the first contact plug partially filling the contact hole, a metal silicide layer on a surface of the first contact plug, and a second contact plug on the metal silicide layer and partially filling the remaining portion of the contact hole.

Abstract: A random noise evaluation method is comprised of: capturing and obtaining current image data; calculating a difference between the current image data and an average of previous image data; calculating a current difference square sum using a sum of the difference and a previous difference square sum; and calculating a random noise value using the current difference square sum. Since a noise evaluation algorithm obtains random noises without storing image data for all pixels of a*b*n, it is able to evaluate random noise evaluation for a high-resolution image sensor even with a relatively small size of memory.

Abstract: A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.

Abstract: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.

Abstract: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

Abstract: A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed.

Abstract: A system-on-chip includes: a controller generating a first input/output control signal determining an input/output state in a normal mode, a second input/output control signal determining the input/output state in a sleep mode, a normal value, and a sleep value; stored in first through fourth registers; a first selector selecting the first or second input/output control signals depending on operation mode; an internal logic circuit operating in the normal mode and generating a signal to be transferred to an external chip based on the normal value; and a second selector selecting an output from the fourth register or the internal logic circuit depending on the operation mode; a power manager controlling the first and second selectors; and a retention input/output device storing outputs of the first and second selectors when the normal mode turns to the sleep mode, which are held when transitioning from the normal to sleep mode.

Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.

Abstract: A source driver output circuit of a thin film transistor (TFT) liquid crystal display (LCD) includes first through n-th voltage generators, first through n-th switching portions, first through n-th sub switching portions, and a switching circuit. The voltage generators receive first through n-th corresponding input voltages and generate first through n-th sub input voltages. The switching portions generate the sub input voltages as first through n-th corresponding output voltages when activated, or cut off the sub input voltages when deactivated. The sub switching portions connect predetermined share lines to the output voltages when activated, or cut off the predetermined share lines when deactivated. The switching circuit maintains each of the share line voltages equally at an intermediate voltage level that is between the share line voltages. Therefore, the slew rate of a signal input to the panel from the source driver can be improved, and current consumption in the source driver can be reduced.

Abstract: A multibit electro-mechanical memory device and a method of manufacturing the same include a substrate, a bit line in a first direction on the substrate, a lower word line in a second direction intersecting the first direction, a pad electrode isolated from a sidewall of the lower word line and connected to the bit line, a cantilever electrode expending in the first direction over the lower word line with a lower void therebetween, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a trap site expending in the second direction over the cantilever electrode with an upper void therebetween, and an upper word line to which a charge to curve the cantilever electrode in a direction of the trap site is applied, and on the trap site.

Abstract: A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure.

Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.

Abstract: There is provided a CMOS image sensor and an electronic product using the same. The CMOS image sensor includes a plurality of pixels for embodying colors having different wavelengths. Each of pixels includes a buried barrier layer disposed in a semiconductor substrate and having a barrier potential energy of a conduction band thereof at an equilibrium state, a first layer disposed at a main surface of the semiconductor substrate separated from the buried barrier layer in a vertical direction and having a first potential energy of a conduction band thereof at the equilibrium state, and a second layer disposed between the first region and the buried barrier layer having a second potential energy of a conduction band thereof at the equilibrium state. The second potential energy is higher than the first potential energy and the barrier potential energy and a thickness of the second layer is thicker as the wavelength is longer.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

Abstract: Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {?1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i?2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i?1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i?2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.