Abstract: Problem analysis system, given either half of a cause-effect relationship, automatically formulates a natural language or Boolean query that is automatically submitted via a knowledge search tool to a database of cause-effect relationships, and responses to this query from the database are automatically provided.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: In a device and a method for detecting a letter box for an MPEG decoder, the method includes performing processing area filtering for selecting a processing area of an image used to detect the letter box; performing intra-macroblock filtering for determining the letter box area based on a change level of pixels in macroblocks in one line of the image from the processing area; performing impulse data filtering for excluding the line being detected a high frequency component from the determined letter box area; performing inter-macroblock filtering for determining the letter box area based on a change level of lines between macroblocks of the image; performing inter-line filtering for determining a boundary of the letter box based on an average of the pixel values of the lines; and performing inter-picture filtering for outputting a boundary value of the letter box that has the highest frequency number as the boundary of the letter box in successive images.

Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

Abstract: In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge of a first clock signal and holds a result of the sampling. The delay circuit receives and delays the first clock signal by a predetermined delay time and outputs a second clock signal. The FIFO device processes the result of the sampling output from the first sampling circuit using a FIFO method in response to a first edge of the second clock signal output from the delay circuit.

Abstract: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Abstract: A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

Abstract: In a composition for removing a polymeric contaminant that may remain on an apparatus for manufacturing a semiconductor device and a method of removing a polymeric contaminant using the composition, the composition includes from about 5 to 10 percent by weight of a fluoride salt, from about 5 to 15 percent by weight of an acid or a salt thereof, and from about 75 to 90 percent by weight of an aqueous solution of glycol. The composition can effectively remove the polymeric contaminant from the apparatus within a relatively short period of time, and suppress damages to parts of the apparatus.

Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

Abstract: A method and apparatus for writing data to and reading data from a phase-change random access memory (PRAM) include encoding original data using a predetermined encoding function, selecting data, from among the original data and the encoded data, which require less power when being written to the PRAM, writing the selected data to the PRAM, generating marking information related to the selected data, and writing the marking information to the PRAM. Therefore, power consumption can be reduced when data are written to the PRAM.

Abstract: Provided is an electrostatic discharge (ESD) protection diode including: a well formed of a first conductivity in a semiconductor substrate; an active region that is formed of a second conductivity in the well and includes a plurality of first active lines extending in a first direction; a sub-region of the first conductivity including a plurality of first sub-lines extending in the first direction, the first sub lines being formed in the well, arranged to surround an outer region of the first active lines, and arranged in alternation with the first active lines; a device isolation region separating the active regions and the sub-regions; a plurality of active contacts arranged in a row in the active regions; and a plurality of sub-contacts arranged in a row in the sub-region.

Abstract: A multibit electro-mechanical memory device and a method of manufacturing the same include a substrate, a bit line on the substrate; a lower word line and a trap site isolated from the bit line, a pad electrode isolated from a sidewall of the trap site and the lower word line and connected to the bit line, a cantilever electrode suspended over a lower void in an upper part of the trap site, and connected to the pad electrode and curved by an electrical field induced by a charge applied to the lower word line, a contact part for concentrating a charge induced from the cantilever electrode thereon in response to the charge applied from the lower word line and the trap site, the contact part protruding from an end part of the cantilever electrode, and an upper word line formed with an upper void above the cantilever electrode.

Abstract: There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.

Abstract: Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.

Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.

Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.

Abstract: Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.

Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.