Abstract: In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.

Abstract: A memory subsystem couples to a double wide word bus in common with a number of central processing units for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes common control circuits, timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom into a pair of data registers. The outputs of the data registers couple to the inputs of a pair of output multiplexer circuits. The outputs of the multiplexer circuits are connected to provide double wide output to the double wide word bus.

Abstract: Soft error rewrite control apparatus is included within a memory system for rendering the semiconductor memory modules less susceptible to single bit errors produced by alpha particles and other system disturbances. During a number of successive memory cycles occurring at a predetermined rate, the soft error rewrite control apparatus enables the read out of information stored within each module location, the correction of any single bit errors contained therein and the rewriting of the corrected information back into such location. Diagnostic apparatus is further included which is connected to place the memory system in a state for testing and verifying the operation of the soft error control apparatus. Also, the diagnostic apparatus is connected to condition the soft error control apparatus for operating in a high speed mode enabling the read out correction and rewriting of each location to take place within a minimum amount of time.

Abstract: Firmware is provided to change, upon execution, information in the system base which is located in both main memory and internal scratch pad registers.Hardware structures controlled by a microprogrammed control store, which provides for the generation of signals causing the creation of an image in main memory of a communication center comprised of registers at another location in the central processing unit. The microprogrammed control store further generates signals which causes the interchange of the information between the communication center and its image.

Abstract: In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit.

Abstract: A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.

Abstract: A programmable communications processor is coupled to execute instructions of programs designed to process the transfer of information between a plurality of communication channels and a main memory included in the system. A software implemented and controlled pause counter enables the execution of a given maximum number of instructions for servicing, for example, a communication channel following which it suspends or pauses such servicing, in order to service another higher priority request which may be pending. Processing of lower priority service requests thus cannot delay the recognition and handling of higher priority requests for more than a minimum period of time and the effective throughput rate is increased.

Abstract: A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

Abstract: The present invention relates to document positioning and feeding apparatus for high speed printers, such as normally associated with data processing systems. The document feeding apparatus is particularly adapted to provide high quality, high speed printing of stock consisting of multiple pages or non-uniform thicknesses. It is useful for the printing of savings-books, checks and statement of account forms. The apparatus utilizes a unique coupling means to maintain equal and opposite rotation of the feeding elements and to substantially reduce relative rotary motion between the feeding elements during the feeding of stock into the printer. Novel support means allow the feeding elements to accommodate stock having a different thickness for one part of the stock compared to another part.

Abstract: A logic memory addressing system requiring minimal central processing unit (CPU) control is provided for extending the memory addressing capacity of a CPU. A logic control system simplistic in design and including a logic decoding unit responds to control words issued by the CPU by way of control and address busses to randomly access memory words, and to effect the exchange of information between the memory unit and a data bus.

Abstract: A quick disconnect male terminal is disclosed having a stem which is inserted into a circular hole in the printed circuit board prior to wave soldering the terminal to the printed circuit board. The terminal is designed to use minimal material, to use little surface area on the printed circuit board, and be easily assembled into printed circuit boards. The terminal stem is embossed with a V-shape to increase its strength and to increase the solder wicking action through the hole in the printed circuit board. The tip of the V-shaped terminal stem protruding through the hole in a printed circuit board may also be flattened as a means of affixing the terminal prior to wave soldering.

Abstract: An apparatus and method for determining whether test probes of a test fixture on an automatic test equipment (ATE) device are in contact with the intended test points on an electronic assembly under test. The undetected failure of the test probes to contact the test points on the electronic assembly test, such as a printed circuit board can result in meaningless test results or lead to unnecessary further testing or replacement of nonfaulty components that tested as failed. The apparatus and method are directed to detecting which test probes are not in contact with their corresponding test points on the electronic assembly undergoing test by ATE.

Abstract: A logic control system in a video display terminal is disclosed for synchronizing the operation of dual, asynchronously operating CRT control unit semiconductor chips to accommodate a substantially increased number of visual attributes per display row with minimal effect on data character transfer rates.

Abstract: A method for determining whether test probes of a test fixture on an automatic test equipment (ATE) device are in contact with the intended test points on an electronic assembly under test. The undetected failure of the test probes to contact the test points on the electronic assembly test, such as a printed circuit board can result in meaningless test results or lead to unnecessary further testing or replacement of nonfaulty components that tested as failed. The method is directed to detecting which test probes are not in contact with their corresponding test points on the electronic assembly undergoing test by ATE.

Abstract: A tape device adapter logic control system is disclosed for accommodating the transfer of control information and data of variable formats, densities, and logic level conventions between a medium performance device controller (MPDC) and mass storage devices. Information recorded in one processor code may be converted for use in a data processor having any other processor code, and may be packed or depacked to accommodate a change in density. Tristate logic is used to provide recursive data paths, thereby accommodating plural functions with minimal duplication of logic devices.The MPDC loads control information into a device command register and an adapter command register of the tape device adapter to respectively provide control commands to device controllers and to the logic control system. The adapter command register controls the data flow through the tape adapter, and the operation of logic devices in the flow path to effect a 1.times.1, 4.times.3, 8.times.5, or 8.times.

Abstract: In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.

Abstract: An automatic purge control for a banknote dispensing system including an operator panel having a keyboard for initiating transaction requests, a dispensing chamber adjacent to the panel for receiving banknotes dispensed in response to an operator request, a lockable access door to enable the operator to gain access to the chamber to remove dispensed notes, and a tiltable platform positioned within the chamber for discharging dispensed notes from the chamber under predetermined purge conditions detected by a microprocessor within the system. The microprocessor calls for a purge operation when it has been determined that the operator has either failed to remove dispensed notes or has left notes within the chamber. A purge operation may also be performed as a result of a system failure, such as a power outage or a counting error occurring during a dispense cycle; or when a foreign object is detected in the dispensing chamber as a result of vandalism.

Abstract: A badge reading system is provided which includes a badge having embedded therein bistable magnetic wires arranged in BCD encoded logic patterns, and a badge reader for reading the bistable magnetic wire patterns to form an information stream. As the badge is inserted within the badge reader housing, the movement of the badge is sensed at initial, intermediate and full insertion points along the insertion path. A logic control system of the badge reader operates in concert with the sensors and a bistable magnetic wire detector to protect against data errors which may occur because of incorrect badge orientations and insertions, and counterfeit badges.

Abstract: A data processing system remote monitor interface includes a first device which transmits different types of time-related information signals along multiple parallel channels to a second device for reception and combination into a different number of information signal outputs. The different types of digital information signals are synchronized by the first device prior to transmission to the second device. Components in the first device, the multiple parallel channels, and the second device are selected to maintain signal synchronization by minimizing signal skew thereby eliminating the necessity for signal resynchronization in the second device. The second device includes a receiver section which has a plurality of receivers. Each receiver operates to receive only one digital information signal and to pass the received signal onto its output.

Abstract: Device for detecting the direction and change of rotational speed of a rotating element. In one embodiment, a pair of phototransistors which are energized by a light source according to an ordered sequence through a disk formed by opaque and transparent sectors coupled to the rotating element. The two phototransistors controls, when energized the switching on of two transistors which enable the discharge of two capacitors, charging with a predetermined time constant in the interval time between discharges. The discharge control action of one of the two phototransistors on a first capacitance is however conditioned by the charge level reached by the other capacitance and therefore both by the order in which phototransistors are energized and by the energization frequency. If the energization frequency is lower than a certain limit or the energization order is not the correct one, the first capacitor reaches a charge level higher than a reference value and supplies an indication signal accordingly.