Abstract: An adapter includes free running low power clock circuits connected to provide a time of day value accessible by a central processing unit which couples to the adapter through a controller subsystem. The adapter cicuits are constructed on a circuit board which is installed as part of the controller subsystem. The clock circuits are connected to one terminal of a battery power supply whose other terminal connects to an interface connector included within the adapter. Upon installing the adapter board in the subsystem, the battery power supply is connected to provide power for operating the clock circuits. When the adapter is removed from the subsystem, the battery power supply is disconnected, preventing it from discharging. The adapter includes an adapter connector for connecting the output terminal of the battery power supply to enable the battery to be charged or its power level monitored when the adapter circuit board is installed.

Abstract: A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes detection apparatus for detecting a conflict condition resulting in an improper assignment. The detection apparatus, upon detecting such a condition, advances the relacement circuits forward for assigning the next sequential group of locations or level inhibiting it from making its normal location assignment.

Abstract: A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes control apparatus, an instruction buffer for storing instructions received from main store and a transit block buffer comprising a plurality of locations for storing read commands. The control apparatus includes a plurality of groups of bit storage elements corresponding to the number of transit buffer locations. Each group includes at least a pair of instruction fetch indicator elements which are operatively connected to control the writing of first and second blocks of instructions into the instruction buffer.

Abstract: A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.

Abstract: A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes an instruction buffer having first and second sections for storing instructions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each location is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location.

Abstract: A data processing system having a control store storing firmware words for controlling the system, logic for executing logical operations on input data, including the performing of a first and second data processing routine, and apparatus for addressing the control store to access selected firmware words to control the execution of desired logical operations on the input data. The system operates in a particular mode of control to suspend the operation of the first routine in order to execute the second routine whereby the logical apparatus includes a register for saving a return address associated with the last instruction of the first routine. When the system terminates the second routine and restores the first routine to operation, the contents of the save register are employed, with the lowest order bit thereof inverted, to access the control store to fetch the firmware word used to reenter the first routine.

Abstract: An automatic cash depository having a tiltable feeding mechanism which receives an inserted deposit envelope and delivers it to a collection bin. Controls are provided for maintaining the feeding mechanism in a first position representing a blind feed path which does not present access to the collection bin. After the deposit envelope has fully entered the feeding mechanism and the insertion slot has been closed by a rotatable bolt closure, the control tilts the feeding mechanism and causes the envelope to be delivered to the collection bin.

Abstract: The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.

Abstract: Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a second address location of the random access memory. The mantissa result is truncated by addressing the high order 24 bits at the first address location and the 48 binary ZEROs at the second address location.

Abstract: A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed.

Abstract: A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two delay lines to form a compensation network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.

Abstract: Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus requests received from various units desiring to use the common buses. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the multiple common buses.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

Abstract: Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. A counter in the adapter starts to count when the adapter receives a digital signal. The count is transferred to a register and the counter presets when the adapter receives the next digital signal. The count is indicative of the time between the successive digital signals and should be representative of multiples of an integer. The count signals stored in the register address a read only memory whose output signals preset the counter to a value to compensate for the difference between the expected time and the actual time between the successive digital signals thereby reducing the read error rate.

Abstract: Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enable the paths accessed by the automated maintenance system and to control the conditions of operation of the central processing unit. A control point register stores control point information from the central processing unit indicating its internal status. This information is read and displayed by the automated maintenance system. Address and data registers serve to buffer data and addresses exchanged between the automated maintenance system and the CPU. The disclosed interface apparatus allows a general utility automated maintenance system to be adapted to test a specific central processing unit.

Abstract: A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches.

Abstract: A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit (CPU) in executing tasks. The real time adapter unit includes a microprocessing section, a timer section, and a module time of day section. The time of day includes circuits which are connected to provide accurate and reliable time of day values. The timer module section includes circuits which are connected to provide variable time intervals. The circuits of both sections are connected to the circuits of the microprocessing section.

Abstract: If the firmware calls for an operand rounding operation, apparatus in the Scientific Instruction Processor (SIP) tests the bit to the right of the low order bit of the normalized operand to determine if a rounding cycle is required. If the operand requires a normalization cycle or a mantissa overflow correction cycle, the rounding operation is performed in those cycles.

Abstract: A Scientific Instruction Processor (SIP) uses a Programmable Read Only Memory (PROM) to control the output of a two stage shifter. The shifter performs the necessary mantissa shift operations of shift right, shift left, shift right around, as well as inserting certain constant information into the system. Control signals and shift signals applied to the input address terminals of the PROM select the PROM output signals which enable the selected mantissa hexadecimal digits which output the shifter. This forces hexadecimal digits from the enabled positions and hexadecimal ZERO digits in those positions not enabled.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.