Abstract: A communication processor is coupled to recognize and handle on a priority basis, service interrupt requests from a plurality of communication line adapters. The processor is also adapted to perform a firmware-controlled scan of the communication line adapters, completely independently of any data transfers involving such adapters, to determine the status of the communication lines handled thereby and, on detection of a status which is changed from a previously stored status, to store the new status in the processor and take any action necessary as indicated by a command previously stored in the processor.

Abstract: A data processing system employing firmware for executing a self test routine each time the system goes through the power-up cycle. The self test firmware provides for compilation of a system configuration map during each execution so that configuration and status data is made available for accessing by the system operation firmware and application software. This enables external systems to set appropriate interrupt vectors and levels and to arrange their physical I/O and device handlers so that various devices within the local system can be accessed. The routines performed in the self test operation include a CPU test, a RAM test, a real time clock test, a communication controller loop-back test, a ROM signature calculation, a controller I/O test, a system configuration map compilation, and a status display routine.

Abstract: A hardware logic timing system for a tape device adapter is disclosed for accommodating the exchange of control information and data between a medium performance device controller (MPDC) and mass storage devices. Plural timing frequencies exhibiting selectively variable phase relationships are provided for increased operating mode flexibility. More particularly, 1.times.1, 4.times.3, 8.times.5, 8.times.7 or 8.times.9 data packing or depacking operations with or without code conversion are supported during both data reads and data writes.The logic timing system is responsive to the MPDC and each of the mass storage devices, and may operate in clear, wait, normal or burst modes to preserve information integrity while maintaining commercially acceptable transfer rates.

Abstract: A printed circuit card enclosure is disclosed having end plates and shelf members which are secured together to form the enclosure. The shelf members are provided with holes for receiving flexible snap-in card guides which are used to retain and support printed cards within the enclosure. The shelf members and card guides are further designed such that in a card enclosure designed to retain multi-levels of printed circuit cards, a single shelf member may be shared between two adjacent levels of printed circuit cards and the card guides installed within a single set of holes with the upper card guide being used to retain the lower edges of printed circuit cards in the upper level and the lower card guides being used to retain the upper edges of printed circuit cards in the adjacent lower level.

Abstract: Firmware generated commands provided by a control store in a microprogrammed communications processor which is coupled in a system including a main memory and a central processing unit control the processing of instructions from the central processing unit, interrupts from the communications channels and servicing of such channels if a channel status change is detected. The firmware also controls the operation of the servicing of such channels by providing a control mechanism by which data is read from or written into the main memory. Further, interrupts which are not handled immediately are handled in a deferred interrupt arrangement.

Abstract: Information from a document is read by a reader sorter; the information is organized in fields including a transit field which is made up of 8 decimal digits and a check digit. The 8 decimal digits are each multiplied by a predetermined number which depends on the position of the decimal digit in the transit field as indicated by a position counter. Signals indicative of the decimal digit and the position in the transit field are applied to the address terminals of a Programmable Read Only Memory (PROM). Each address location stores the units position of the product of the multiplication of the decimal digit times the predetermined value. A firmware routine stored in a control memory performs the check digit calculation "on the fly" using the units position of the product from the PROM and certain status bits stored in a scratchpad memory.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract: In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.

Abstract: In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

Abstract: A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digits from the operand into words containing a maximum of 8 decimal digits for transfer to the execution unit. The execution unit processes the words in accordance with a decimal numeric instruction. The throughput of the system is increased when processing short operands which contain 15 decimal digits or less by apparatus in the decimal unit which detects the short operand and determines the number of cache memory cycles between the cycle the first word of the short operand is received from cache memory and the cycle on which the first assembled word is transferred to the execution unit for processing.

Abstract: A generalized event management architecture based upon an analysis of the traditional interprocess communication and synchronization mechanisms is disclosed. An extended semaphore architecture is proposed which combines the properties of Dijkstra's semaphore with that of a trap facility. This model is further developed into a more general architecture capable of handling complex events, structured event condition variables and generalized assignments. The architecture is defined in terms of entity classes, relationship classes and functional primitives. Finally a typical hardware computer system utilizing these concepts is shown and described.

Abstract: One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.

Abstract: Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in either a frequency modulation (FM) mode or a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. Apparatus converts the time between successive digital signals into PROM addresses. The PROM address locations store coded signals identifying the data as binary ONE or binary ZERO signals.

Abstract: An automatic purge control for a banknote dispensing system including an operator panel having a keyboard for initiating transaction requests, a dispensing chamber adjacent to the panel for receiving banknotes dispensed in response to an operator request, a lockable access door to enable the operator to gain access to the chamber to remove dispensed notes, and a tiltable platform positioned within the chamber for discharging dispensed notes from the chamber under predetermined purge conditions detected by a microprocessor within the system. The microprocessor calls for a purge operation when it has been determined that the operator has either failed to remove dispensed notes or has left notes within the chamber. Interlocks are provided on the purge apparatus for inhibiting continued operation of the dispensing system if a purge cycle is improperly executed.

Abstract: A memory subsystem couples to a single word bus in common with a central processing unit for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which specifies the row of chips to be accessed within a first one of the pair of memory units. The subsystem further includes control circuits, common timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom.

Abstract: A method and apparatus for detecting a deadlock condition where two or more processes are waiting for events which cannot happen. Firmware is provided to examine the request of a first process of a group of processes for assignment of a first resource of a group of resources, and to determine whether said first resource is or is not currently assigned to a second process of said group of processes which said second process is already waiting directly or indirectly for a second resource of said group of resources which said second resource is currently assigned to the said first process.

Abstract: In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

Abstract: A badge reader logic system is provided for receiving binary coded information read from a badge, card or other recording medium having data encoded thereon by means of bistable magnetic wire patterns, and reformatting such binary coded information into a two-dimensional data matrix row and column format for processing by a local controller. The binary coded information further is interrogated in time relation with logic signals received from sensors placed along an insertion path of the badge into the badge reader to detect unauthorized badges, incorrect badge orientations and other error conditions.