Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

Abstract: Apparatus for intercepting a channel program that is operative with a particular input/output device when an input/output device of higher priority requests service. The channel program is intercepted at a time when the processor is required to process a minimum of information. This enables the processor to be readily operative with the original input/output device.

Abstract: A paging apparatus includes addressing hardware for addressing a number of physical devices coupled to various communication buses, for mapping virtual addresses to real addresses, and controlling the flow of data. The paging apparatus generates 8 control signals, 5 of which modify a virtual address into a real address of a memory thereby expanding the capabilities of the real address from 256 address locations by an additional 512 address locations. The remaining 3 control signals control the flow of data by enabling or disabling data control apparatus in the physical devices.

Abstract: A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit in executing tasks. The real time adapter unit includes microprocessing circuits and clock circuits. These circuits are connected to provide accurate and reliable time of day values in response to commands from the central processing unit.

Abstract: There is disclosed herein an apparatus for computerized real time verification of the correctness of pin locations for wire wrap connections made by human operators in constructing or upgrading computer backplanes. A suitably programmed microprocessor operates from a data base consisting of the information from a wire list drawing fed into the microprocessor's memory from a cassette tape record. The microprocessor is linked to the backplane to be verified and to the hand operated wire wrap gun serving as the test probe by a uniquely designed Wire Check System Interface. Both wire adds and wire deletes may be made.

Abstract: In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which, in response to a microword indicating that the result of the decimal numeric calculation is a short operand, that is, a predetermined number of words or less, and in accordance with an instruction descriptor, generates a count of the number of words of the resultant operand the decimal unit will transfer to memory.

Abstract: Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.

Abstract: Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.

Abstract: Apparatus for resolving the priority of a plurality of input/output devices. The device request signals and signals indicating the channel number of the currently active channel program are applied to the address terminals of a programmable read only memory. Each address location stores bits indicative of the next priority device for the given input conditions.

Abstract: A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes apparatus operative in response to a first predetermined type of command specifying the fetching of data words to set an indicator flag to a predetermined state.

Abstract: In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which is conditioned by the instruction descriptors in advance of receiving the operands to align the decimal digits of the operand words as the words are received by the apparatus from memory.The descriptor information for each operand includes the scale factor, the position of the sign, the position of the most significant character within the word, whether it is a floating point or scaled operand, the number of bits in each decimal character, either 4 or 9 bits, and the length of the operand.The apparatus is conditioned by the descriptor information to align the two operands for processing.

Abstract: A memory subsystem includes a memory board comprising of a number of memory chips positioned at a corresponding number of physical row locations. The memory chips are one of two types selected to provide a predetermined memory capacity. The board further includes a number of decoder circuits connected to generate a corresponding number of sets of chip select signals in response to address signals applied thereto. These signals are applied through corresponding sets of logic circuits for application to the memory chips of each row. Additionally, logic gating circuits logically combine predetermined chip select signals for generating additional chip select signals. These additional chip select signals are applied through switches, the outputs of which are applied to predetermined ones of the sets of logic circuits. When the switches are positioned in a predetermined manner, the additional chip select signals are directed to only predetermined one of the physical row locations via the sets of logic circuits.

Abstract: Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a data phase.

Abstract: An improved large capacity air distribution system for cooling electronic components mounted on printed circuit boards. The system has an air plenum chamber of substantially constant rectangular cross section. Openings are formed in the side walls of the chamber to permit air from within the chamber to flow outwardly in a direction substantially normal to the outer surfaces of the side walls and over the components to be cooled. A baffle in the form of a tapered wedge formed from a pair of thin metal baffle sheets is mounted in the plenum chamber so that the joined edges of the metal baffle sheets are positioned centrally in the air inlet of the chamber and the baffle is otherwise symmetrically disposed in the chamber. A large number of small round holes are formed through the sheets of the baffle, the area of the holes occupying a substantial percentage, approximately 36 percent, of the total area of the baffle. A high capacity air pump supplies air under pressure to the interior of the plenum chamber.

Abstract: A hardware/firmware communication line adapter for interfacing a communication processor to a broadband high level data link communication channel. Transmit and receive data and control characters received either from the processor or from a communication channel device are processed under the control of the adapter firmware to effectuate CRC checking, byte size control, extended and variable field format control, partial last byte control, and block transfer control functions on the transmitted/received data stream. First-in-first-out (FIFO) buffer memories are employed in the transmit circuits to queue a frame of transmit data and control characters at the adapter whereby the communication processor/adapter interface control is simplified. Similarly, a FIFO buffer is employed in the receive circuits to reduce the frequency of receive interrupts and to enable block transfer of received data to the processor.

Abstract: An impact matrix printing head for use in a computer printer. The printing head utilizes a unique design to provide an unitary needle guiding assembly and an unitary electromagnet assembly which can each be independently removed from the printer head without the need to disassemble. The printer head includes adjustments for the air gap of the electromagnet assembly and adjustments for the needle position, both initially and after needle wear has occurred.

Abstract: A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.

Abstract: Information from a main data processor is transferred to an auxiliary data processor of the system and is stored in a control file which may be addressed by either a firmware word from a control store or by use of the function code received in an instruction from the main processor. Information in such control file is used for the purpose of addressing main memory. The address for main memory may be incremented or decremented simultaneously as operands are being fetched from main memory for execution.

Abstract: A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer system. An additional feature of this hardware is increased speed and efficiency in addressing when the computer system is operating normally.

Abstract: A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required number of horizontal and vertical paths to be connected to all of the integrated circuit chips to be positioned and interconnected thereon. The required holes for such integrated circuit chips when drilled include first sets of holes for mounting groups of integrated circuit chips required for implementing a first group of features and which are to be interconnected to the other integrated circuit chips of the subsystem mounted on the different sections of the board. Second sets of holes are included on the board so as to have a predetermined relationship with the first sets of holes for mounting alternative groups of integrated circuit chips to be interconnected in a manner to implement other features.