Abstract: A method of connecting an incoming call to one of a plurality of call responsive apparatus all of which are associated with a single directory number, comprised of determining which one of the call responsive apparatus answered an immediately preceding call, and ringing the one call responsive apparatus as a signal to respond to the incoming call.

Abstract: A system for transmitting FM signals comprised of apparatus for receiving an input data signal, apparatus for precompensating the received data signal, apparatus for applying the precompensated data signal to a constant envelope modulator to provide a modulated signal, apparatus for applying the modulated signal to a power efficient non-linear amplifier and transmitting a signal resulting therefrom, apparatus for receiving the transmitted signal in an I-Q receiver, and apparatus for filtering the received transmitted signal for the precompensation, to obtain an output data signal representative of the input data signal.

Abstract: A method of repeating a pulse signal comprised of outputting a signal at a first voltage level upon a first rising edge of the pulse signal exceeding a low threshold, then raising the threshold and outputting the signal at another voltage level upon a second trailing edge of the pulse signal dropping below the raised threshold. An improved VLSI circuit has at least one conductive track containing distributed parasitic elements, the track being divided into two or more separate segments, a repeater connecting each of the segments, and apparatus for modulating the threshold of the repeater prior to and/or during the interval of a pulse carried by the track.

Abstract: The present invention relates to a method of encoding speech comprised of processing the speech by harmonic coding to provide, a fundamental frequency signal, and a set of optimal harmonic amplitudes, processing the harmonic amplitudes, and the fundamental frequency signal to select a reduced number of bands, and to provide for the reduced number of bands a voiced and unvoiced decision signal, an optimal subset of magnitudes and a signal indicating the positions of the reduced number of bands, whereby the speech signal may be encoded and transmitted as the pitch signal and the signals provided for the reduced number of bands with a bandwidth that is a fraction of the bandwidth of the speech.

Abstract: A DRAM having a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low resistance power supply conductors extending in parallel with the row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across the chip accessible to the sense amplifiers, apparatus for coupling sense inputs of the sense amplifiers to the power supply conductors, and apparatus coupling the sense amplifier enabling signal conductors to the apparatus for coupling sense inputs, for enabling passage of current resulting from the logic high level and low level voltages to the sense amplifiers.

Abstract: A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.

Abstract: A far infrared (FIR) to near infrared (NIR) light converter is comprised of a quantum well intersubband photodetector (QWIP) integrated vertically with a light emitting diode (LED).

Abstract: A low noise dual polarization electromagnetic power reception and conversion system is disclosed. It comprises a first plurality of conducting elements performing a bandpass function on incident waves, a second plurality of antenna units, located behind the first elements, performing a power reception and conversion function, and a third plurality of conducting elements located behind the antenna units, performing a bandstop function on incident signals. A layer of lossy material is optionally disposed behind the third elements to absorb any wave passing through them. This system can be used to achieve high efficiency power reception and conversion and also reduce levels of radiation of both harmonics of the powering frequency and intermodulation products formed by nonlinear mixing of signal wavefields from other users of the radio spectrum with the powering signal wavefield.

Abstract: A waste water reuse system comprised of a first holding tank for disposition above the toilet tank of a conventional toilet, the holding tank having a waste water inlet located adjacent a top thereof, an overflow outlet located below the waste water inlet, a removable filter disposed within the holding tank between the inlet and outlet in a position to filter water incoming from the inlet, a gravity fed outlet at the bottom of the tank for connection to a water inlet of the conventional toilet, a water supply inlet at or adjacent the bottom of the tank for connection to a fresh water supply, and a float valve connected to the water supply inlet for controlling inflow of fresh water to the holding tank, the float valve having a float ball for causing shut-off of the supply of fresh water at a level substantially below the overflow outlet, and apparatus connecting the waste water inlet to a bathtub water outlet.

Abstract: A holster assembly for retaining a radio pager or data receiver including a clip fixed to the assembly having a first position for resiliently clamping the holster assembly to an article of clothing and another stable open position for supporting the assembly on a surface as a stand for the pager or receiver, a vibrator alert apparatus and a battery connected thereto contained wholly within a housing formed by the holster assembly.

Abstract: A complementary metal oxide silicon (CMOS) data to emitter coupled logic (ECL) data translator system comprised of translator apparatus for receiving data signals from a CMOS circuit powered from a CMOS voltage power source, apparatus for powering an ECL circuit from the power source, a transmission line carrying output signals from the translator apparatus to the ECL circuit, having a predetermined characteristic, a load having the characteristic impedance connecting the transmission line to the power source, and the translator apparatus comprising apparatus for outputting a data signal on the transmission line which corresponds to the received data signals but having an amplitude compatible with the ECL circuit and referenced to a voltage of the power source.

Abstract: A method of enabling a controllable and variable number of bits to be written to a group of cells of a DRAM or SRAM simultaneously in a block, wherein a predecoded column address signal is decoded for enabling writing to cells of the DRAM or SRAM, and the predecoded column address signal is block overwritten by means of a block address signal, whereby plural decoders are enabled simultaneously for simultaneous writing to a column of cells notwithstanding the logic levels of the predecoded address signal.

Abstract: A random access memory chip is comprised of static random access storage elements, word lines, and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer is comprised of in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing a same operation function on each bit of the data in parallel to provide a result.

Abstract: A retainer for a flat object comprised of an envelope having front and rear planar members forming a pocket open at one end and for containing the flat object, and joined along opposite side edges, the planar member having a centrally located tongue projecting forward of the one end, the tongue being resiliently bendable adjacent the front end around an end and under a contained object so as to lie against an inside surface of the rear planar member, the width of the tongue being a fraction of the width of the planar members, the inside width of the envelope between the side edges being wider than the flat object by a distance sufficient to lift the tongue from under the contained object when the edges of the envelope are compressed toward each other and toward adjacent edges of the contained object.

Abstract: A method of receiving a data signal in a radio transceiver by passing an input receive signal through an input bandpass filter having a bandwidth sufficient to reject signals with frequencies equal to or greater than the receive signal frequency plus a first intermediate frequency (IF) signal frequency plus a first standard IF signal frequency and also to reject signals with frequencies less than the receive signal frequency minus twice the first IF frequency, and downconverting the input filter filtered input receive signal by the transmit frequency to produce the first IF signal. The first IF signal is filtered in an LC filter, and the filtered first IF signal is mixed with a local oscillator signal having a difference frequency therefrom which is equal to the first standard IF frequency to produce the first standard IF signal.

Abstract: A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.

Abstract: Method of providing closed captioned data to a television viewer comprised of detecting closed captioned data signals transmitted in conjunction with a television signal, decoding the data signals to caption display signals, and displaying the caption display signals on an auxiliary screen separate from a screen displaying the television signals.

Abstract: The present invention relates to a method of data assembly for distribution of the data via a mass audience distribution system, comprised of storing in a random access memory packets of data which are to be transmitted to the audience, storing in a first address table a sequence of memory addresses of the data for transmission of the data in the sequence, progressively reading the first table to retrieve the addresses of those packets of data that are to be transmitted to the audience in the sequence, reading the memory to retrieve the packets of data in the sequence, and transmitting the read packets to the audience in real time.

Abstract: A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) is comprised of providing a sequence of data pulses and a sequence of reference clock pulses, resetting the phase locked loop to force the VCO to its lowest operating frequency, releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, detecting the presence of data pulse transitions, in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and outputting output clock pulses from the phase locked loop.

Abstract: A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) including a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch.