Abstract: A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the computer and the programming apparatus. A first component used to encode programming instructions and configuration data to form a first transmission stream that is transmitted to the programming apparatus in a single, long burst. The programming apparatus includes a second component of the software architecture that interprets the first transmission stream and programs the PLD using, for example, Boundary-Scan signals that are generated in response to the programming instructions and configuration data. A buffer memory stores data shifted out of the PLD during the programming operation, which is transmitted to the computer in a single, long burst after the first transmission stream is completed.

Abstract: A hybrid interface apparatus including a fixed base including a contact-locking structure supporting several spring-based contact members, and a nesting member slidably positioned over the fixed base and having a central test area that includes an array of through-holes that are aligned with upper ends of the contact members. To facilitate testing of ICs including both relatively low-speed general-purpose I/O structures and new high-speed I/O structures, the contact members mounted on the contact structure include both low-cost, relatively high-inductance contact members for facilitating communication with the general-purpose I/O structures of the IC, and relatively expensive, low-inductance contact members for facilitating high-speed communications with the high-speed I/O structures of the IC.

Abstract: A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device arranged in the order in which the devices are chained in the system. The device identification codes are then used to automatically retrieve device specifications from a central database. When no identification code is provided from the device, or the database fails to include specifications for a particular device, the user is prompted to enter minimum information or specifications necessary to carry out communications with the device. After device specifications are entered for each device, the user is prompted to enter configuration data, which is automatically matched to its associated device, and compared for consistency with the device specifications.

Abstract: Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.

Abstract: A method for concurrently programming a series of in-system devices by grouping the devices into sequentially-programmed groups, wherein a best possible grouping of devices is determined that achieves a minimum total configuration time. When a system includes multiple devices, it is sometimes more efficient (i.e., requires less total configuration time) to program the devices in two or more groups, as compared to programming all of the devices at the same time (i.e., as a single group). The method utilizes device information to identify an optimal or best grouping by comparing the total configuration times of several possible groupings, and selecting the grouping having the lowest total configuration time. Once a best grouping is determined, programming is performed by selecting a first group from the grouping and programming the first group while bypassing devices all other groups. Once the first group is programmed, a next group is programmed, and so on.

Abstract: A light curtain safety system for a semiconductor device handler that includes a programmable control unit and a robot mechanism that is selectively operated in response to signals generated by the control unit. The light curtain safety system includes an apparatus for generating a light curtain such that accessing the robot mechanism requires breaking the light curtain. The light curtain safety system detects an operating state of the semiconductor device handler using signals generated in the control unit, and allows de-activation of the light curtain apparatus only when operating state of the semiconductor device handler is in a predetermined “safe” operating state. When the light curtain apparatus is active and the light curtain is broken, the light curtain safety system causes the semiconductor device handler to terminate power flow to the robot mechanism.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: A channel-based network includes a system server, one or more Internet sites and one or more user terminals. The system server stores a series of computer pages and a master channel table that includes a list of channel numbers. Channel numbers and logo spaces are purchased by Internet sites wishing to be included in the network. The system server operator updates the computer pages to include logos for the Internet sites, and updates the master channel table each time a channel number is purchased. The updated web page and master channel table information is then downloaded to the user terminals of the network.

Abstract: A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a partitioned memory configuration is implemented to backup the data word and its associated error correction code to the non-volatile memory. In this way the non-volatile memory is able to store a range of counts whose maximum number far exceeds the memory's endurance limit.

Abstract: An actuator including a pneumatically distended elastomer membrane that is pressurized and depressurized using electrostatically actuated flap valves laminated onto a printed circuit board. The flap valves close only at zero pressure gradients and flows so that elevated closing and hold-off pressures are achieved. Fluid expelled from the elastomer membranes during collapse are vented through a wall of the actuator. An air jet object mover utilizes an array of the pneumatic actuators as valves to open and close air jet vents. A fiber optic micro-switch utilizes pneumatic actuators to position a mirror.

Abstract: A stress-balancing layer formed over portions of a spring metal finger that remain attached to an underlying substrate to counter internal stresses inherently formed in the spring metal finger. The (e.g., positive) internal stress of the spring metal causes the claw (tip) of the spring metal finger to bend away from the substrate when an underlying release material is removed. The stress-balancing pad is formed on an anchor portion of the spring metal finger, and includes an opposite (e.g., negative) internal stress that counters the positive stress of the spring metal finger. A stress-balancing layer is either initially formed over the entire spring metal finger and then partially removed (etched) from the claw portion, or selectively deposited only on the anchor portion of the spring metal finger. An interposing etch stop layer is used when the same material composition is used to form both the spring metal and stress-balancing layers.

Abstract: A release mechanism for manually securing a pluggable fiber optic transceiver to a cage mounted on a host circuit board. The release mechanism includes a pivoting faceplate connected to a transceiver housing such that the faceplate is rotatable from a first position in which the faceplate is positioned over a front surface of the housing to a second position in which the faceplate is pivoted away from the front surface of the housing. The release mechanism also includes a lever that disengages a boss from an opening formed in a resilient transceiver latch of the cage when the faceplate is in the second position. In one embodiment the boss is mounted on the housing, and the lever pushes the transceiver latch away from the boss. In another embodiment, the boss is mounted on the lever.

Abstract: Scanning probe systems, which include scanning probe microscopes (SPMs), atomic force microscope (AFMs), or profilometers, are disclosed that use cantilevered spring (e.g., stressy metal) probes formed on transparent substrates. When released, a free end bends away from the substrate to form the cantilevered spring probe, which has an in-plane or out-of-plane tip at its free end. The spring probe is mounted in a scanning probe system and is used to scan or otherwise probe a substrate surface. The probes are used for topography, electrical, optical and thermal measurements.

Abstract: A complimentary non-volatile memory (CNVM) cell includes an n-channel transistor and a p-channel transistor that have drains connected like a CMOS inverter, and that are controlled by a shared floating gate and a shared control gate. The CNVM cell is programmed by band-to-band tunneling (BBT) electrons generated in the source of p-channel transistor, and is erased by BBT holes generated in the source of n-channel transistor (or by back tunneling of electrons from the floating gate). Read out is performed using a select transistor connected to the drains of the n-channel and p-channel transistors.

Abstract: A channel-based network for accessing the Internet including a system server, one or more Internet sites and one or more user terminals that are connected via the Internet. The system server stores a master channel table that includes a list of channel numbers, each channel number having an associated Internet address and an associated Internet site name. Each Internet site of the network is addressable by an associated Internet address stored in the master channel table. Each user terminal automatically (i.e., without user participation) downloads and stores a local copy of the master channel table. The channel numbers and associated Internet site names are read from the downloaded local copy of the channel table and displayed, for example, on a television in a menu-like manner. The user selects an Internet site name from the displayed menu, and enters the channel number associated with the selected Internet site name using an input device that is similar to a television remote control.

Abstract: A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the comparator circuit is used to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. The high or low comparator output signal is transmitted to the switch control circuit, which utilizes a pair of level shifters to control the pair of PMOS switches, which in turn couple one of the first and second voltage sources to the output node.

Abstract: Low voltage sensing circuits for non-volatile memory (NVM) devices including a comparator (operational amplifier) having input terminals connected to the gate terminals of first and second PMOS transistors. The PMOS transistors are coupled between a system voltage source and respective bit lines carrying cell and reference currents from a selected NVM cell and a reference NVM cell, respectively. To facilitate low system voltages, voltage supply or source-follower circuits are connected between the gate and drain terminals of each PMOS transistor such that the bit line voltages are increased without increasing the voltage signals applied to the input terminals of the comparator, and without the use of charge pumps.

Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed form necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.

Abstract: A channel-based network user terminal including a set-top box, a display, and input devices. A non-volatile memory stores a semi-permanent copy of a channel table downloaded from a server via the Internet. The channel table includes a list of channel numbers, associated Internet site names, and associated Internet addresses. A volatile memory stores a temporary copy of the channel table during user sessions. The channel numbers and associated Internet site names are read from the volatile memory and displayed as a menu. A user selects an Internet site name from the menu, and enters the channel number associated with the selected Internet site name using a numeric keypad provided on a remote control input device. The user terminal then accesses the selected Internet site by reading the Internet address associated with the entered channel number from the volatile memory, and transmitting the Internet address onto the Internet.

Abstract: Scanning probe systems, which include scanning probe microscopes (SPMs) are disclosed that include cantilevered spring (e.g., stressy metal) probes and actuation/position sensing electrodes formed on a substrate. The actuation electrodes are used to position the spring probe relative to the substrate using electrostatic, magnetic, acoustic, or piezoelectric arrangements. An actuation signal source is switched between full on and off states to facilitate “ON/OFF” probe actuation in which the spring probe is either fully retracted against the substrate or deployed for scan operations. The position sensing electrodes are used to sense the deflected position of the spring probe relative to the substrate using resistive, magnetic, or piezoresistive arrangements. Spring probe arrays are disclosed that include multiple spring probes arranged on a single substrate.