Abstract: An ornament having a printed insert bearing a personalized message or picture that is suspended within a transparent bulb. The printed insert is produced by printing the personalized message or picture onto transparency paper using a computer and color printer, and cutting the transparency paper to form a disk-shaped insert that is sized to fit within the transparent bulb. The printed insert is then curled and inserted through the opening of the transparent bulb, and is then suspended within the transparent bulb from a cap using a hitch pin (fastener).

Abstract: A first in, first out (FIFO) memory system and method in which the full or empty condition of the FIFO memory is detected before the FIFO memory is actually full or empty, thereby allowing the generation of FULL or EMPTY control signals immediately after a last data value is written into or from the FIFO memory. An almost-empty condition, is detected by comparing the read address and write address values. When the read and write address values indicate that one data value remains in the FIFO memory and a read operation is about to be performed, an ALMOST_EMPTY control signal is applied to a data input terminal of a first register that is clocked by a read clock signal. The ALMOST_EMPTY control signal is latched by the first register at the next rising edge of a read clock signal, thereby causing the register to generate a high EMPTY control signal in the same read clock cycle during which the last data value is read from the FIFO memory.

Abstract: A reticle that is modified to prevent bridging of the masking material (e.g., chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

Abstract: A power-on reset (POR) circuit that delays de-assertion a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset. During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a delay period whose length is determined, in part, by the amount of noise in the applied power. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.

Abstract: A color CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. A silicon-nitride layer is deposited on the upper surface of the pixels, and is etched using a reactive ion etching (RIE) process to form microlenses. A protective layer including a lower color transparent layer formed from a polymeric material, a color filter layer and an upper color transparent layer are then formed over the microlenses. Standard packaging techniques are then used to secure the upper color transparent layer to a glass substrate.

Abstract: A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions, and a pre-metal dielectric structure formed over the polysilicon gate structure. The pre-metal dielectric structure is a triple layer structure including a lower Borophosphosilicate glass (BPSG) layer formed over the polysilicon gate structure, a Nitride layer formed on the lower BPSG layer, and an upper dielectric layer (e.g., BPSG or USG) formed on the Nitride layer. The Phosphorous concentration in the lower BPSG layer is greater than the Phosphorous concentration in the upper dielectric layer, thereby providing retention protection for the underlying memory structures while facilitating optimal chemical mechanical polishing (CMP) planarization characteristics.

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.

Abstract: A method for implementing a CAM function using a dual-port RAM. Data is stored in the memory array of the dual-port RAM as decoded “one hot” data words such that each data word is stored in one column, and each data word includes only one logic “1” bit value. Data match operations are then performed by reading a row of memory cells of the memory array in response to a match data word. If the row contains one or more of the logic “1” bit values, then the match data word matches (is equal to) one or more of the decoded “one hot” data words. One input port of the dual-port RAM is configured to automatically write decoded “one hot” data words into the memory array by accessing a selected memory cell in response to an X+Y-bit word. The encoded X+Y-bit word is transmitted to an address terminal of the first input port, and a logic “1” bit value is transmitted to a data input terminal of the first data port.

Abstract: A programmable logic device (PLD) structure that combines the AND/OR structure of a CPLD with the look-up table (LUT) -based logic structure of a field programmable gate array (FPGA) to implement both wide logic functions and complex logic functions in a single pass. In one embodiment, a CPLD includes a programmable AND array, a programmable OR array, and several look-up tables (LUTs) that are connected to receive product-terms from the programmable AND array and sum-terms from the programmable OR array. The programmable AND array is programmable connected to multiple input lines, and the programmable OR array is programmably connected to receive selected product-terms generated by a group of AND gates of the programmable AND array. Each LUT includes memory cells that are addressed by the sum-term and product-term applied to the LUT input terminals.

Abstract: A measurement system is provided for measuring Vil and Vih of integrated circuits (ICs). The measurement system includes a computer that transmits a control signal to a power supply, which in turn transmits a corresponding applied voltage to the input terminal of an IC. The output terminal of the IC is connected to a parallel port of the computer, thereby forming a feedback loop that allows automatic measurement of Vil and Vih.

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.

Abstract: A semiconductor device tester and handler interface includes tester and handler boards with a coplanarity plate between them. The handler board includes a central area adapted to mount semiconductor devices to be tested by a tester. The tester board has tester contacts located to interface with a tester. During cold testing, to avoid condensation on the side of the handler board away from the devices being tested, dry gas is applied to the region formed by the coplanarity plate. During hot testing, flowing dry gas prevents the hot handler board from excessively heating the tester board and associated tester.

Abstract: An apparatus and method for testing “chip scale” integrated circuits (IC's) using a vertical probe card mounted on a printed circuit board (PCB). A nesting assembly mounted over the vertical probe card includes alignment walls and an alignment plate including chamfered through holes. The alignment walls are slanted to provide rough alignment of the IC within the nesting assembly, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Tips of formed wire probes extend from the vertical probe card towards the bottom surface of the alignment plate. When the alignment plate is pushed towards the vertical probe card by a device handler, the tips of the wire probes extend through the through-holes and pierce the solder balls of the IC, providing electrical contact between the IC and the PCB.

Abstract: A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.

Abstract: A voltage regulator circuit in an integrated circuit (IC) device such as a Complex Programmable Logic Device (CPLD) comprises a reference voltage generator, a tuning circuit, and an output driver circuit. The reference voltage generator converts an external supply voltage provided to the IC device into a stable reference voltage. The tuning circuit converts the stable reference voltage into a desired internal supply voltage, such as the reduced voltage required by deep sub-micron transistors. The output driver circuit provides the desired internal supply voltage with sufficient current to properly power the circuits of the IC device. The tuning circuit includes an op-amp and resistive elements configured in a voltage divider configuration in the negative feedback loop of the op-amp. The output of the op-amp can be set to the desired internal supply voltage by properly sizing the resistive elements.

Abstract: During the development of process parameters for fabricating an integrated circuit, a test circuit is provided on the wafer that provides rapid identification of process problems (i.e., before failure analysis), detects defects down to a part-per-million (PPM) level, and identifies the precise location of any defects, thereby facilitating rapid failure analysis during the development and refinement of IC fabrication processes used to fabricate an integrated circuit (IC). In a first embodiment, the test circuit includes parallel conductive paths that are selectively connected to a signal source by pass transistors. Open circuits are identified by sequentially connecting one end of the conductive paths to the signal source and measuring the current at the other end. In a second embodiment, the test circuit includes perpendicular sets of overlapping conductors. Short conductive segments extend in parallel with a first set of conductors that are electrically connected to a second set of conductors.

Abstract: A PLD includes buffered interconnect resources and configurable logic circuits that are controlled by data stored in a configuration memory. Each buffer of the buffered interconnect resources includes a feedback pull-up transistor. To avoid crowbar current problems, a high voltage is transmitted to the input terminals of all buffers before configuration, thereby biasing all buffers into a high feedback voltage mode. In one embodiment, the high voltage is transmitted to the buffers using a global control signal that forces all output drivers to generate high output voltages, and then turning on all pass transistors of the interconnect resources to broadcast the high voltages to every buffer. After configuration, the global control signal is de-activated. In another embodiment, each buffer circuit includes a second pull-up device that is turned on at power-up to force all buffers into the high feedback mode.

Abstract: A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

Abstract: An FPGA configuration circuit including a mask register that stores mask data during configuration memory read-modify-write operations. The mask data enables a multiplexing circuit to overwrite selected memory cells in a configuration memory array with new data bit values. Data bit values from all other memory cells in the configuration memory array are fed back by the multiplexing circuit. In one embodiment, the new data bit values are transmitted on a bi-directional bus and stored in a shift register. The configuration memory array is arranged in frames that are addressed by a frame address register, and the contents of an addressed frame are written to a shadow register. Under the control of the mask register, the multiplexing circuit modifies the frame data bit values stored in the shadow register using the new data bit values stored in the shift register. The contents of the shadow register are then written into the addressed frame.

Abstract: An on-chip method for self-modifying a programmable logic device (PLD) including a plurality of configurable logic blocks (CLBs), a plurality of interconnect resources for selectively connecting the CLBs, and a block memory circuit selectively connected to the interconnect resources. The CLBs are configured to implement a reconfigurable functional portion and a configuration control portion. A logic function is performed by the reconfigurable functional portion in accordance with first configuration data, while the configuration control portion monitors operation data signals transmitted to or from the reconfigurable functional portion. When the configuration control portion detects a need to modify the configuration of the reconfigurable functional portion, the configuration control portion transmits read instructions (e.g.