Abstract: Improved pixel circuits are disclosed for high fill-factor large area imager systems using continuous (e.g., amorphous silicon) sensor layers. A first approach prevents crosstalk by ensuring that each pixel is not able to go into saturation. A second approach employs a cascode transistor to maintain the bias of the sensor contact at a constant potential regardless of illumination condition. These two approaches may be combined. A resistive film connecting the pixel contacts may be used in conjunction with the second approach to prevent aliasing of signal and noise.

Abstract: A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device arranged in the order in which the devices are chained in the system. The device identification codes are then used to automatically retrieve device specifications from a central database. When no identification code is provided from the device, or the database fails to include specifications for a particular device, the user is prompted to enter minimum information or specifications necessary to carry out communications with the device. After device specifications are entered for each device, the user is prompted to enter configuration data, which is automatically matched to its associated device, and compared for consistency with the device specifications.

Abstract: An image sensor is disclosed including passivation walls extending above the pixel contact pads into a photosensor layer (e.g., amorphous silicon) such that the pixel contact pads are isolated to reduce cross-talk. The passivation walls are formed from SiO2 or SiON to further reduce cross-talk. An embodiment includes metal structures provided under interface regions (e.g., under the passivation walls) separating adjacent pixels that are negatively biased to prevent cross-talk, and optionally extend under the contact pad to increase pixel capacitance. One embodiment omits p-type dopant from the lower amorphous silicon photodiode layer, and additional photodiode material layers are disclosed. Another disclosed sensor structure utilizes a textured surface to increase light absorption. A color filter structure for image sensors is also disclosed.

Abstract: A bottle warmer for warming a beverage (e.g., baby formula or milk) stored in a disposable baby bottle assembly including a disposable liner supported in a hollow sleeve (holder). The bottle warmer includes a heat transfer element that enters a lower opening of the bottle sleeve and contacts the liner. In one embodiment, the heat transfer element includes a cylindrical wall that slides between the sleeve wall and the liner to facilitate faster heating. The bottle warmer also includes a portable (e.g., gas or electric) heat generating system that heats the heat transfer element, which in turn heats a beverage stored in the liner.

Abstract: Methods are disclosed for fabricating spring structures in which a passive, conductive coating is deposited onto the spring structure before release. A release layer is deposited on a substrate and then a spring metal layer is formed thereon. A first mask is used to form a spring metal finger from these layers. A second mask defines a window exposing a tip of the finger. The release layer under the tip is etched through the window, and then a passive-conductive coating material (which may also have spring characteristics) is deposited on the tip. The second mask and residual coating material are then lifted off, and a third (release) mask is formed that is used to release a free end of the spring metal finger. The release mask is then stripped. When the passive-conductive coating includes spring characteristics, the stress variations of the coating help to lift the free end if the finger during release.

Abstract: Scanning probe systems, which include scanning probe microscopes (SPMs), atomic force microscope (AFMs), or profilometers, are disclosed that use cantilevered spring (e.g., stressy metal) probes formed on transparent substrates. When released, a free end bends away from the substrate to form the cantilevered spring probe, which has an in-plane or out-of-plane tip at its free end. The spring probe is mounted in a scanning probe system and is used to scan or otherwise probe a substrate surface. A laser beam is directed through the transparent substrate onto the probe to measure tip movement during scanning or probing. Other detection schemes can also be used (e.g., interferometry, capacitive, piezoresistive). The probes are used for topography, electrical, optical and thermal measurements. The probes also allow an SPM to operate as a depth gauge.

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.

Abstract: A BGA-type capacitor structure including a conventional chip capacitor mounted on the upper surface of an inexpensive substrate, and having solder balls mounted on a lower surface of the substrate. Lands that are required to mount the chip capacitor are formed on the substrate, which is offset from the surface of a PCB by the solder balls. The substrate can be a thin sheet of polyimide tape that is etched or perforated to provide holes through which the solder balls contact the lands used to mount the chip capacitor. An assembly incorporating the BGA capacitor structure includes a PCB having an array of metal vias extending between opposing upper and lower surfaces, a BGA IC mounted on the upper surface and soldered to first ends of the metal vias. The capacitor structures are soldered to contact pads formed on the lower surface of the PCB.

Abstract: A trigger circuit for an In-System Programmable (ISP) memory device that operates with a JTAG interface. The trigger circuit receives instruction signals from the JTAG control circuitry, and limits the duration of these instruction signals to avoid erroneously repeating ISP programming operations. The trigger circuit includes a first logic circuit, a delay circuit, and a second logic circuit. The first logic circuit generates a logic high output when both the JTAG RUN-TEST and a program instruction signal are simultaneously asserted, and causes the second logic circuit to toggle the limited duration instruction signal into a logic high state. The delay circuit also detects the simultaneous assertion of the JTAG RUN-TEST and a program instruction signal, and generates a cancellation signal after a predetermined number of clock cycles. The cancellation signal causes the second logic circuit to toggle the limited duration instruction signal into a logic low state.

Abstract: A method for dynamically burn-in testing a PLD by either configuring or fabricating the PLD to implement a self-executing logic operation that automatically and repeatedly turns on and off selected transistors of the PLD using only static test signals. The self-executing logic operation implemented by the PLD includes a driving logic function (e.g., an oscillator) and a driven logic function (e.g., a counter). The PLD is placed on a conventional load board and heated in a conventional oven while static test signals are applied to selected terminals of the PLD through the load board, thereby causing the PLD to implement the self-executing logic operation.

Abstract: A portable speech therapy device that enables post-operative cancer patients to practice voice exercises without direct supervision by activating a series of colored indicator lights in predetermined patterns associated with push-button actuation switches. The patient is initially taught to make a certain sound when an associated indicator light is turned on, and then allowed to practice with the device at home. The sequences associated with each actuation switch are made progressively more challenging as the patient masters the sequences associated with each switch (e.g., progressively shorter time periods allowed response, progressively greater number of prompts, or different patterns in which the colored indicators are turned on). The device is field programmable to allow the doctor to tailor sequences to correspond with a patient's recovery progress.

Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

Abstract: Patterned ground planes are formed between out-of-plane microcoil structures and underlying integrated circuits (ICs). Each out-of-plane coil includes a series of loops extending from base (contact) pads formed on a dielectric layer (e.g., thick IC passivation, or BCB formed on thin passivation). Losses due to capacitive coil-to-substrate coupling are minimized using a central ground plane structure located under the base pads of the microcoil. Magnetic losses are reduced by forming a low-resistance ground plane structure including end portions located outside of the ends of the microcoil. The low-resistance ground plane can be slotted to reduce the loop size of eddy current pathways. The low-resistance ground plane is formed from one or more of the top IC metal layers, copper pads formed between the IC passivation and the dielectric, portions of the metal used to form the microcoil, or combinations thereof.

Abstract: A fieldless CMOS image sensor that include a non-LOCOS isolation structure surrounding the photodiode diffusion region of each pixel. The isolation structure is formed by an anti-punchthrough (APT) implant isolation region formed in the substrate around the photodiode diffusion region, and spacer oxide that is formed using a special mask to cover the APT implant region. The APT implant isolation region is self-aligned with the special spacer oxide mask. A width of the isolation structure between two adjacent photodiodes is 0.5 &mgr;m or more. Similarly, LOCOS structures that are used, for example, in the image sensor active circuitry, are separated from the image-sensing (e.g., photodiode) region of each pixel by portions of the isolation structure having a width of 0.5 &mgr;m or more.

Abstract: A beverage container including a body and a lower cap having a cooling element mounted thereon that extends into an interior portion of the body. The lower cap is removable for convenient charging (e.g., freezing) of the cooling element. The lower cap is then attached to the body and liquid is inserted into the body through an upper opening. A mixing fixture is integrally formed on the free end of the cooling element, and is used to mix the cooled liquid stored in the body with a powdered substance entered through the upper opening. In one embodiment, the beverage container is a multi-chambered container that includes a rotatable hollow member for storing the powdered substance, and a housing for securing the hollow member to the body such that a curved wall of the hollow member separates the powdered substance from the cooled liquid stored in the body.

Abstract: Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.

Abstract: An inner stripe laser diode structure for GaN laser diodes is disclosed. Inner stripe laser diode structures provide a convenient means of achieving low threshold, single mode laser diodes. The structure of an inner stripe laser diode is modified to produce lateral index guiding.

Abstract: A system server for a channel-based network including one or more Internet sites and one or more user terminals. The system server includes a channel table database storing a master channel table that includes a list of channel numbers, each channel number having an associated Internet address and an associated Internet site name. Each Internet site of the network is addressable by an associated Internet address stored in the master channel table. The system server includes a network database and an update manager database. The system server identifies each user terminal requesting service by comparing transmitted identification information with authorized user information stored in the network database. The system server also compares a channel table version number from the requesting user terminal with a version number stored in the update manager database that is associated with the master channel table, and notifies each requesting user terminal when updated channel table information is available.

Abstract: A reticle (mask) that is modified to prevent bridging of the masking material (e.g., chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

Abstract: A method and assembly for testing multiple IC packages for solder joint fractures that occur in response to thermal cycling. A test PCB is fabricated with contact pads arranged to match a BGA IC package footprint, wherein pairs of the contact pads are linked by conductive traces (lines) to form a lower portion of a daisy chain. The BGA IC package is modified to link associated pairs of solder balls, e.g., using wire bonding to form an upper portion of the daisy chain. Mounting the BGA IC package on the test PCB completes the daisy chain. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked by wire bonding, the daisy chain provides a conductive path that passes through all solder balls of the BGA IC package.