Abstract: A floating gate memory device that includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative pole of a driver circuit). The switching circuit includes two switches respectively connected between the two negative voltages and the common node. Each of the switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources. An optional triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the switches that includes a deep N-well region biased by a system voltage source (e.g., VCC) to reverse bias the central P-well region.

Abstract: A floating gate memory device that includes a column latch circuit that is isolated from a series of bitlines by PMOS pass transistors controlled by a bitline latch switch circuit. The bitline latch switch circuit selectively applies either +5 V or −2 V signals to the gate terminals of the PMOS pass transistors, thereby allowing the PMOS pass transistors to selectively pass 0 (zero) Volts during, for example, program operations. A −2 V charge pump is activated to generate the −2 V signal during operations requiring 0 Volt bitline voltages, and is turned off during all other operations.

Abstract: A method for producing a color CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. A silicon-nitride layer is deposited on the upper surface of the pixels, and is etched using a reactive ion etching (RIE) process to form microlenses. A protective layer including a lower color transparent layer formed from a polymeric material, a color filter layer and an upper color transparent layer are then formed over the microlenses. Standard packaging techniques are then used to secure the upper color transparent layer to a glass substrate.

Abstract: A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits are located at the ends of the diffusion bits lines that selectively connect the diffusion bit lines to a bit line decoder circuit to read appropriate signals from selected memory cells. A series of metal jumpers extend over and connect the ends of the diffusion bit lines. By connecting both ends of the diffusion bit lines together, the metal jumpers allow the diffusion bit lines to be longer without increasing resistance, so that a single pair of column select circuit control a large number of memory cells to increase the area efficiency of the memory array. Conversely, the metal jumpers reduce the resistance in shorter diffusion bit lines, thereby increasing memory array endurance.

Abstract: A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry, and input signals to the array are routed onto bit lines that are also connected to the product term generation circuitry.

Abstract: An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected to the bus including a frame data register, a frame address register, a control register, a command register, and an optional data check register. The bus interface generates control signals in response to the address field and the operand field that cause one or more registers to perform predefined operations according to subsequent data words in the bit stream. For example, during configuration write operations, the bus interface enables the frame data register to receive data signals that are subsequently transferred to a configuration memory array.

Abstract: A Java-based method for performing Boundary-Scan Test procedures on an IEEE Standard 1149.1 compliant integrated circuit device. A Boundary-Scan Test application procedural interface (BST API) is provided that includes several objects defining the Boundary-Scan architecture of IEEE Standard 1149.1 compliant integrated circuit devices, and defines a plurality of Java-based source code commands utilized in applets for performing Boundary-Scan Test procedures. To facilitate implementing a single applet on a wide variety of hardware platforms, the BST API is based on a command structure subset implemented by a wide range of available Java flavors.

Abstract: A cyclic redundancy check (CRC) register is connected to the bi-directional bus and a packet processor in a configuration circuit of an FPGA. The CRC register performs transmission error detection functions based on the command/data transmissions to various registers connected to the bus, and based on the address information transmitted from the packet processor to an address/operand decoder used to enable the various registers to receive subsequent command/data words. The CRC register calculates a check-sum value in accordance with a predetermined equation. At any time during the transmission (e.g., halfway through configuration or at the end of configuration), a pre-calculated check-sum value is transmitted to the CRC register that represents an expected check-sum value at the selected time. The pre-calculated check-sum value is then compared with the check-sum value currently stored in the CRC register.

Abstract: A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations.

Abstract: Disclosed is a safe connector including a casing, a plurality of conducting elements, a protecting board, an elastic device, and a locking device. The casing has an opening. The plurality of conducting elements are set in the casing for conducting electricity. The protecting board is set in the casing for protecting the conducting elements from being touched. There are a plurality of holes set on the protecting board, and each of them corresponds to one of the conducting elements for passing the conducting elements therethrough. The elastic device is set between the casing and the protecting board for urging the protecting board against the opening, and a locking device is set in the casing for locking the protecting board in the casing.

Abstract: A method for forming a CMOS image sensor cell such that stress is minimized in regions surrounding the light sensitive (e.g., photodiode) portion of the cell, thereby reducing leakage current and minimizing white spots in CMOS image sensors. The field oxide surrounding the light sensitive region is formed with interior angles greater than 90° and/or is continuously curved. The reset gate is offset from the light sensitive regions of active pixel cells by a distance greater than 0.25 &mgr;m. A mask is used during n+ doping of the light sensitive region to shield an inner edge of the surrounding field oxide and extends 0.5 &mgr;m or more over the light sensitive region. A mask is provided over the interface between the field oxide and the light sensitive region during sidewall spacer formation. A metal structure contacting the light sensitive region is spaced 0.4 &mgr;m or greater from the surrounding field oxide.

Abstract: A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semiconductor substrate faces the protective substrate. With the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns. A transparent substrate (e.g., glass) is then secured to the backside surface of the semiconductor substrate, thereby sandwiching the semiconductor substrate between the transparent substrate and the protective substrate.

Abstract: A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semiconductor substrate faces the protective substrate. With the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns. A transparent substrate (e.g., glass) is then secured to the backside surface of the semiconductor substrate, thereby sandwiching the semiconductor substrate between the transparent substrate and the protective substrate.

Abstract: A fault tolerance method for FPGAs featuring interconnect resources made up of wiring segments that are programmably coupled to two or more configurable logic blocks (CLBs) through connection switches. In accordance with a first embodiment, one of the wiring segments is designated as being reserved for each CLB. During routing, a wiring segment is assigned to a signal path only if the signal path is not associated with signal transmission to or from the CLB to which the wiring segment is reserved. In accordance with a second embodiment, one or more connection switches are designated as reserved switches for each horizontal segment. During routing, the reserved switches are not used to route signal paths. Fault tolerance is then performed by shifting the logic portion assigned to a defective CLB and/or the associated switch configuration data along its row towards a spare CLB located at the end of the row.

Abstract: A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations.

Abstract: A semiconductor device tester and handler interface includes a tester and handler board. The board includes multiple test sites and has multiple layers of metallization traces. The handler side of the board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester side of the board has tester contacts located to interface with a tester. Vias connect metallization traces in one metallization layer to metallization traces in another layer. The traces and vias are arranged to form paths from a tester contact to a test socket. The test sites are placed close to and sometimes superimposed on the tester contacts receiving the test signals. Thus delay is minimized and with multiple test sites, throughput is increased.

Abstract: An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path.

Abstract: A voltage regulator circuit in an integrated circuit (IC) device such as a Complex Programmable Logic Device (CPLD) includes a reference voltage generator, a tuning circuit, and an output driver circuit. The reference voltage generator converts an external supply voltage provided to the IC device into a stable reference voltage. The tuning circuit converts the stable reference voltage into a desired internal supply voltage, such as the reduced voltage required by deep sub-micron transistors. The output driver circuit provides the desired internal supply voltage with sufficient current to properly power the circuits of the IC device. The tuning circuit includes an op-amp and resistive elements configured in a voltage divider configuration in the negative feedback loop of the op-amp. The output of the op-amp can be set to the desired internal supply voltage by properly sizing the resistive elements.

Abstract: A core-based PLD programming method for programming a PLD to implement a user-defined logic operation including a set of cores. The PLD includes several configurable logic blocks (CLBs). Each core includes several logic portions that are arranged in a fixed pattern, and each logic portion includes configuration data for configuring one CLB. A placement process is performed during which only a single reference logic portion of each core is placed in a configuration data table to form a first placement pattern. Non-reference portions of the cores are not placed in the configuration data table during the initial placement process. An annealing process is then performed during which the reference logic portions associated with the cores are moved between CLB sites in an attempt to identify an optimal placement solution. A separate CLB site overlap table is utilized to keep track of the non-reference logic portions during the annealing process.

Abstract: A method and structure for testing static signal levels on an integrated circuit device using an electron beam deflection device. Each static signal is applied to a first terminal of a switch, such as an AND gate, an OR gate, or a pass transistor. An alternating control signal of approximately 1 MHz is transmitted to a second terminal of the switch such that the switch generates an output signal that is either constant (if the static signal is at a first level), or has a frequency equal to that of the alternating control signal (if the static signal is at a second level). The output signal is transmitted to a pad located on an exposed surface of the integrated circuit, where an electron beam deflection device is utilized to determine the static signal level by detecting the presence or absence of an alternating signal. A method for determining the voltage level of a signal includes applying the signal to the gate of a transistor and an alternating control signal to an input terminal.