Abstract: Efficient methods are disclosed for fabricating spring structures in which a passive, conductive coating is deposited onto the spring structure after release. A release layer is deposited on a substrate and then a spring metal layer is formed thereon. A first mask is then used to etch the spring metal layer to form a spring metal finger. A second (release) mask is then deposited that defines a release window used to remove a portion of the release layer and release a free end of the spring metal finger. The second mask is also used as a mask during the subsequent directional deposition of a conductive coating material on the cantilevered tip of the finger. The second mask is then stripped, and the residual coating deposited thereon is lifted off. The resulting spring structure includes conductive coating on the upper surface and front edge of the finger tip.

Abstract: A fiber-optic microswitch is disclosed that includes a flexible mirror positioning structure including an outer fixed frame, a movable platform upon which a mirror is formed, and two or more resilient support members (e.g., monocrystalline silicon springs or torsion beams) connecting the movable platform to the fixed frame. Stationary fibers are mounted over the mirror. An electromagnetic drive mechanism is provided for positioning the movable platform relative to the fixed frame. The electromagnetic drive mechanism includes one or more coils formed on a drive substrate mounted under the monocrystalline structure, and one or more pole pieces that are mounted on the movable platform. Currents are selectively applied to the coils to generate attractive electromagnetic forces that pull the pole pieces, thereby causing the movable platform to move (e.g., tilt) relative to the fixed frame, thereby selectively directing light from one fiber to another. Various monocrystalline structures are disclosed.

Abstract: An interface apparatus including a nesting member having a central test area, a positioning member surrounding the test area, and several removable adapters held by the positioning member to expose a selected portion of the test area. Each removable adapter includes a central opening that is sized to receive a corresponding ball grid array integrated circuits (BGA IC). During a first test procedure, a relatively small BGA IC is inserted through the relatively small central opening of a corresponding first adapter. The first adapter is then removed and replaced with a second adapter having a relatively large central opening. A second test procedure is then performed by inserting a relatively large BGA IC through the relatively large central opening formed in the second adapter.

Abstract: A cage for mounting a pluggable fiber optic transceiver onto a host circuit board. The cage is entirely formed from a single blank, which is folded along predefined fold lines to form top, bottom, and side walls that are secured by a latch. A series of semi-resilient feet extend downward from the cage and are pressed into corresponding plated holes provided in the host circuit board such that the cage is secured to the circuit board without soldering. The feet are integrally formed on the blank during the blank stamping process such that they extend perpendicular to the bottom wall after the folding process. Each foot is has an elongated oval outer edge and defines an eye-shaped opening that facilitates resilient deformation when pressed into the plated holes of the host circuit board.

Abstract: A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (“normal”) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into a special Input/Output Blocks (PC-IOB) of the PLD. When no power control function is needed, a high current output portion of the power control output circuit is deactivated by storing an associated data value a power control configuration memory cell of the PLD, and an output driver of the PC-IOB generates low current output signals on a device I/O terminal. To perform power control functions, a portion of the PLD's programmable logic circuitry is configured to generate a power control data signal, and the high current output portion of the power control output circuit is enabled by storing a corresponding data value in the power control configuration memory cell.

Abstract: A method of fabricating a pack tray is provided wherein a plurality of modules are secured in a master frame. Each pack tray typically includes two types of modules: a chip module having an aperture therein to secure an integrated circuit chip and a pick-up module for picking up the pack tray. In one embodiment, all modules are identical in size. In another embodiment, the modules differ in size.

Abstract: Efficient methods are disclosed for fabricating metal plated spring structures in which the metal is plated onto the spring structure after release. A conductive release layer is deposited on a substrate and a spring metal layer is then formed thereon. A first mask is then used to form a spring metal finger, but etching is stopped before the release layer is entirely removed. A second mask is then deposited that defines a release window used to remove a portion of the release layer and release a free end of the spring metal finger. The second mask is also used to plate at least some portions of the free end of the finger and selected structures exposed through the second mask. Remaining portions of the release layer are utilized as electrodes during electroplating. The resulting spring structure includes plated metal on both upper and lower surfaces of the finger.

Abstract: A method for fabricating IC devices including both rising edge-triggered circuits (e.g., flip-flops or latches) and falling edge-triggered circuits in which a clock signal line is selectively inverted by an on-chip clock signal inverting circuit and applied to one or the other circuit types during test modes. The clock signal inverting circuit is implemented as a two-input exclusive-OR gate, or using a multiplexer. The method includes placing and routing the selected circuit type (i.e., rising or falling edge) such that clock skew is minimized.

Abstract: A sippy cup or other spill-resistant container including a cold plug for cooling liquids placed therein. The sippy cup includes a cup body that surrounds a beverage storage chamber. A bottom wall of the cup body defines an opening. In one embodiment, a support flange extends upward from the bottom wall into the fluid storage chamber and surrounds the opening. In another embodiment, a support flange extends upward through the opening into the fluid storage chamber from a sleeved cap. The cold plug structure includes a tube-shaped body enclosing a refrigerant and having a closed end that extends through the central opening into the fluid storage chamber. A base of the cold plug structure is secured to the bottom wall of the cup body, and is supported by the support flange to prevent displacement of the cold plug caused by dropping or otherwise jarring the sippy cup.

Abstract: A security circuit for an IEEE Standard 1149.1 compliant PLD that is controlled by a security bit or bits programmed when the PLD is incorporated into a final product. The security circuit includes a switch connected directly or indirectly into the Boundary-Scan Register (BSR) chain of the PLD. The security bit applies a control signal to the switch such that test data signals generated during INTEST procedures are either passed through the switch, or blocked by the switch. For example, when the Boundary-Scan architecture of the PLD is set for INTEST procedures when the security bit is set in a first programmed state, the logic gate passes test data from an input terminal to an output terminal. Conversely, when the security bit is set in a second programmed state, the logic gate masks the test data values received at the input terminal (i.e., the shifted test data is blocked).

Abstract: Each pixel of an image sensor array includes a capacitive load that is selectively coupled to or decoupled from the usual sensor capacitance to facilitate dual mode operation. During a first operating mode (e.g., a high-power operating mode such as radiography), a global enable signal is asserted to turn on a mode control transistor of each pixel that couples the selectable capacitive load to the sensor, thereby increasing the total capacitance of the pixels. During a second operating mode (e.g., a low-power operating mode such as fluoroscopy), the global enable signal is de-asserted, thereby decoupling the optional capacitive load from the sensor to minimize pixel capacitance. An amorphous silicon sensor includes an additional metal plate located below the lower sensor plate to provide the optional capacitive load. The additional metal plate is formed from the same metal layer that is used to fabricate the gate lines of the array.

Abstract: A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.

Abstract: A calibration assembly and method for calibrating the device pick-up heads used in multi-head IC handlers such that all of the device pick-up heads are reliably calibrated to a consistent optimal calibration position. Gauge blocks are provided that greatly simplify the calibration process by holding the movable portion of a device pick-up head in an optimal calibration position relative to the base structure of the device pick-up head while the collar is secured. Each gauge block has base portion for supporting the base structure of the device pick-up head, and a flat contact surface against which the lower surface of the movable portion is pressed. The contact surface is a predetermined distance from the base portion such that when the device pick-up head is mounted on the gauge block, the movable portion is maintained in an optimal calibration position relative to the base structure.

Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. For dynamic latching during reading or shifting, each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD.

Abstract: A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being “empty” and “full”, respectively.

Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed from necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.

Abstract: A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

Abstract: A handler interface apparatus for low-temperature semiconductor device testing that includes a bracket and a handler board. The bracket including an outer frame, an inner frame connected to the outer frame by one or more arms, and a cover plate positioned over a central opening of the inner frame. When the handler board is mounted onto the bracket, conductors extending through the handler board from a device contactor pad are enclosed in a chamber formed by the handler board, the inner frame and the cover plate. The handler board is then mated to the test pins of a device tester, which extend through openings located between the inner frame, the outer frame, and the arms of the bracket. During low temperature testing, dry gas is pumped into the chamber through conduits formed in the arms of the bracket to prevent the condensation of moisture on the conductors located in the chamber. In a second disclosed embodiment, a cover plate is attached directly to a handler board.

Abstract: A comparator circuit for detecting full and empty conditions in a first-in first-out (FIFO) memory system. The comparator circuit includes two-input logic circuits for comparing selected read and write addresses. An almost-empty condition is detected by comparing a next-to-be-used read address value with a currently-used write address value. When these address values are equal, high logic signals are passed by a set of mode control multiplexers to the select terminals of a series of carry chain multiplexers, thereby causing a high logic value to be transmitted to a data input terminal of a first register. The first register latches the high logic signal at the next rising edge of the read clock signal, thereby generating a high EMPTY control signal immediately after a final data value is read from the memory.

Abstract: A system and method for operating an asynchronous first in, first out (FIFO) memory system in which the amount of data stored in a FIFO memory is determined by re-synchronizing a binary read address from a read clock signal to a write clock signal, then subtracting the write-synchronized read address from the binary write address. The FIFO memory system includes the FIFO memory, read and write address counters for generating the binary read address and binary write address, respectively, and a write synchronization circuit. The binary read address is converted into a Gray-code value which is then synchronized to the write clock signal. The write-synchronized Gray-code read address value is then re-converted to binary to form the write-synchronized read address.