Abstract: The invention discloses an improved process for forming one or more metal strips on an integrated circuit structure by wet etching of a metal layer which comprises forming an intermediate layer over the integrated circuit structure; forming slots in the intermediate layer; forming a metal layer over the intermediate layer; and wet etching the metal layer sufficiently to remove all metal in the slots while retaining metal on the intermediate layer between the slots to form the desired one or more metal strips. Multiple levels of metal strips may be formed in an integrated circuit structure using the method of the invention.

Abstract: A process is disclosed for improving the isolation between semi-oxide insulated devices, formed on mesa structures. In the fabrication of such devices, a silicon substrate is provided. Patterned regions of one type of conductivity are formed in a major surface of the substrate and an epitaxial layer of silicon is formed on the substrate over the major surface. A patterned mask layer is formed on the epitaxial layer and is etched to expose portions of the epitaxial layer. The exposed portions of the epitaxial layer are removed to form the mesa structures, which overlie the doped patterned regions. Regions of opposite conductivity, called channel stops, are then formed in the substrate between the patterned regions. After filling in the areas between the mesa structures with a field oxide, the devices (bipolar or MOS transistors) are formed on the mesa structures.

Abstract: A CMOS, midpoint sense amplification system for controlling the dynamics of the sense amplification phase of the sense cycle of a CMOS DRAM. The system includes a tracking circuit for initiating the first stage of the sense amplification phase when the differential voltage signal attains a first predetermined value. Circuitry for controlling the sense amplification rate and equalizing current supplied to the source nodes during the first stage is disclosed. In one embodiment, circuitry for detecting when the amplitude of the signal has increased to a second predetermined value and for increasing the sense amplification rate during the second and third stages of the sense amplification phase is disclosed.

Abstract: An improved integrated circuit structure characterized by enhanced step coverage and a method of making it are disclosed. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon having selected portions thereof reacted with a metal capable of forming a metal silicide in situ on the surface of the poly silicon strips, a further oxide layer over the metal silicide, and a metal layer providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer above the poly load resistor. This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure.

Abstract: An elastic buffer includes a memory array for storing received data, each location within the array having an associated cell storing a flag indicative of the most-recently performed (i.e., read or write) on the associated memory location. A potential write overflow of the memory is detected whenever a write attampt is made to a location whose flag indicates a write was most-recently performed. A potential read underflow is detected whenever a read attempt is made to a location when the flag associated with the location next to be read indicates a read was most recently performed. Also, a potential write operation of a memory location prior to the completion of a read on the next location within the array are also generates an overflow/underflow condition. Metastable logic state conditions within the array are avoided because the potential overflow/underflow conditions take cognizance of the finite propogation and setting times of signals within the array.

Abstract: A CMOS data register includes a master stage and a slave stage. The master stage is formed of first transfer gates and first storage devices. The slave stage is formed of second transfer gates, second storage devices and third transfer gates. The transfer gates and storage devices are formed of MOS transistors of one conductivity which decreases layout complexity and reduces the amount of chip area required. The data register is formed of a fewer number of transistor components, thereby reducing the loading on the clock signals.

Abstract: A method and apparatus for aligning projecting parts of an assembly, such as integrated circuit electrical connector pins. A deformation plate at a first deformation station of the apparatus deforms the pins in a first vector direction, e.g., radially outward. At a second deformation station, the apparatus deforms the pins in a second vector direction, e.g., radially inward. The method causes the pins to be aligned to a very narrow tolerance.

Abstract: An apparatus is described for summing the products of a predetermined number of successive pairs of numbers. In the apparatus there is provided an arithmetic unit having a first and a second input and an output, a first, a second and a third register and a first and a second multiplexer. In operation, a first pair of numbers are multiplied and the product thereof stored in the third register. Thereafter, a second pair of numbers are multiplied and the product thereof stored in the second register. Thereafter, the contents of the second and third register are added and the sum thereof stored in the third register. After the sum of the products of the first and second pairs of numbers are stored in the third register, the products of succeeding pairs of numbers are stored in the second register.

Abstract: Methods are set forth for constructing encoding and decoding state machines for preselected variable length fixed rate (2,7) codes. These state machines convert a variable length code to a state dependent fixed length fixed rate (2,7) code. Methods and apparatus are also disclosed for implementing a state dependent fixed length fixed rate (2,7) coding scheme in a manner that is simpler and inherently more reliable than the implementation of the corresponding variable length fixed rate (2,7) code. In addition, the disclosed methods and apparatus for implementing the state dependent code preserve the error recovery features of a variable length fixed rate (2,7) coding scheme.

Abstract: A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.

Abstract: A highly planarized integrated circuit structure having at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with at least one portion defined therein for formation of a source/gate/drain region for an MOS device. All of the contacts of the device are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.

Abstract: A redundancy enable/disable circuit for enabling and disabling subsequently the use of redundant elements includes first through third P-channel MOS transistors, an N-channel MOS transistor, an enable fuse, and a disable fuse. The enable fuse is blown so as to enable the use of the redundant elements, and the disable fuse is blown subsequently to disable use of the redundant elements.

Abstract: A full adder circuit includes a sum circuit section, a carry-out circuit section, a carry-in circuit section; and an output circuit section. The sum circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The sum circuit section also includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order. The carry-out circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The carry-out circuit section also includes a plurality of N-channel MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order.

Abstract: A CMOS high voltage switch for interfaceing between a decoder output and an input to an erasable, programmable read-only-memory includes an inverter for receiving an input signal from the output of the decoder. A N-channel MOS pass transistor has a conduction path and a gate electrode. One end of the conduction path is connected to the output of the inverter, and the other end of the conduction path is connected to an output node. The gate electrode of the pass transistor is connected to a first lower supply potential. A pumping device is connected to the other end of the conduction path for pumping the output node to a first higher voltage during a first mode of operation. A P-channel MOS switching transistor is also connected to the other end of the conduction path for switching the output node to a second lower voltage during a second mode of operation.

Abstract: A highly planarized integrated circuit structure having at least one bipolar device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with openings defined therein respectively for formation of a collector contact region and a base/emitter region for a bipolar device in the substrate. All of the contacts of the bipolar device are formed using polysilicon which fills the defined openings in the field oxide resulting in a highly planarized structure.

Abstract: A dynamic ECL line driver circuit for driving line loads having significant capacitance which includes an input transistor, a reference transistor, a main current source transistor and an emitter follower transistor. The line driver circuit further includes a dynamic current enhancement circuit formed of a buffer portion, a current enhancement portion and a dynamic charge pumping portion. The current enhancement portion includes a current source enhancement transistor and the dynamic charge pumping portion includes a capacitor. The buffer portion is utilized for amplifying and inverting a transient voltage at the collector of the reference transistor. One end of the capacitor is connected to the collector of the reference transistor and the base of the emitter follower transistor, and the other end thereof is coupled to the base of the current source enhancement transistor via the buffer portion.

Abstract: An improved topside sealing of integrated circuit devices is disclosed which provided for hermetically sealing the top surface of the device comprising depositing a sealing layer of a nitride compound directly on the surface to be sealed. In a preferred embodiment, a protective layer may then be deposited over the nitride layer without any intervening masking steps being necessary.

Abstract: The circuit derives Vbep, the base-emitter voltage of a saturated PNP transistor, from the PNP portion of a four-layer (PNPN) silicon-controlled rectifier (SCR) so as to exactly match the characteristics of the PNP portion of an SCR against which the reference voltage is to be compared. The operating point of the SCR in the voltage-reference circuit is adjusted and controlled to duplicate the operating conditions in the circuit to be measured. The voltage between the end layers of the SCR includes the sum of Vbep and Vcen, the collector-emitter drop of the NPN portion of the SCR. The circuit processes this voltage to remove the Vcen term, providing an output voltage which depends upon Vbep.

Abstract: An improved phase detector apparatus which includes a charge pump. The charge pump includes a first integrating node and a second integrating node. The first and second integrating nodes generate node voltages which ramp downward and upward during a given period of a reference signal. When a signal is received to which a reference signal is to be locked on, the integrating sequence of the first and second nodes is altered so that the differential voltage across the nodes indicates a difference in phase between the reference signal and the second signal. A filter is connected between the output signal and the first integrating node, while the second integrating node is referenced to a DC bias level and returns to that level at the beginning and end of each cycle. The charge pump apparatus is driven by variable current sources which give the apparatus a variable frequency response.

Abstract: A machine for applying an adhesive pad to the ends of semiconductor device packages includes a punch assembly, a tape feed assembly, and a package feed assembly. The tape is incrementally fed to the punch assembly where semiconductor packages are individually brought into alignment. The punch assembly first shears an adhesive pad from the tape and thereafter applies the pad to the package. The punch member of the punch assembly includes a resilient tip which assures that the tape is securely attached to the package and helps prevent damage to the package. Semiconductor device packages having such taped ends are less likely to be damaged in subsequent processing and handling.