Abstract: Circuitry, including a non-volatile dynamic random access memory cell, a sense amplifier and a data latch affords non-destructive accessing and comparison of the data stored within the volatile and non-volatile portion of the memory cell. In certain applications, it is desirable to restore the volatile data to the volatile portion of the memory cell, and the circuitry also provides a path for such restoration.

Abstract: A method and device for speeding the transmission and reception of documents by digital facsimile systems employing two-dimensional coding. Information regarding a reference line of a document need not be reaccessed from memory during the processing of the scan line next-following a uni-color reference line. A user-accessible paper-width register utilized in conjunction with a comparator according to the speed-up method permits ready detection of uni-color lines and permits encoding and decoding according to either of two international standards. Utilization of the paper-width register affords ready availability of the accumulated run-length of picture elements within uni-color lines without the need to accumulate the run length or reaccess the uni-color reference line.

Abstract: There is disclosed herein an apparatus and method for generating a first signal related to the rate of change of a second signal. In particular, a system is disclosed for generating a velocity signal in a sampled data servo system. The apparatus uses three track and hold amplifiers one of which is also a difference amplifier to sample the position error signal at selected times. A "present" track and hold amplifier samples and holds the position error signal during the current frame. After this is done, during the same frame, a "summing" track and hold amplifier having its difference inputs coupled to the outputs of the "present" track and hold amplifier and to a "previous" track and hold amplifier samples the difference between the present position error signal and the value of the position error signal during the previous sample frame. This difference divided by the sample period gives the velocity.

Abstract: A logic circuit for activating and deactivating redundant elements include a high-low-high circuit and a dynamic latch coupled to the output of the high-low-high circuit for activating the redundant elements in response to true and complement address signals. The high-low-high circuit includes a first fuse which is blown so as to enable the redundant elements and a second fuse which is blown to disable the redundant elements.

Abstract: A method for forming doped, conductive plugs to fill and planarize contact windows in integrated circuits is disclosed. The process is applicable to CMOS, NMOS and bipolar technologies. Discrete, sized, contact apertures formed superposing junction regions of a substrate are filled with semiconductor material and the semiconductor material is doped to match the conductivity type of the underlying junction regions. Thus, the integrated circuit structure is substantially planarized for formation of interconnect layers.

Abstract: A process is disclosed for filling a trench in an integrated circuit structure without forming a void in the trench which, in a preferred embodiment, comprises partially filling the trench with an etchable material, etching the material in the trench with an etchant capable of removing material adjacent the top of the trench at a rate faster than the rate of removal adjacent the bottom of the trench, and then filling the remainder of the trench with the material; whereby the material deposited adjacent the top of the trench will not close off the trench prior to complete filling of the bottom of the trench with the material.

Abstract: A three-voltage level detector include an input terminal for receiving an input logic signal having either a high level, mid-level or low level voltage. A first level sensing buffer is responsive to the input logic signal for generating a first output sense voltage indicative of whether the input logic signal is either at the (a) high level voltage or (b) mid-level or low level voltage. A second level sensing buffer is responsive to the input logic signal for generating a second output sense voltage indicative of whether the input logic signal is either at the (a) high level or mid-level voltage or (b) low level voltage.

Abstract: An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus used 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: A daisy chain collision detection circuit for use with a StarLAN coded data transceiver includes a voltage comparator having an inverting input, a non-inverting input and an output. The inverting input of the voltage comparator is responsive to differential output voltages from a differential line drive and transient spike voltages from the primary of an isolation transformer. A charging capacitor is connected to the non-inverting input of the voltage comparator. The capacitor is charged to a reference voltage which is directly proportional to the peak voltage of the differential output voltages. The output of the voltage comparator provides an internal collision detection signal which is switched from a high logic level to a low logic level upon the occurrence of a daisy chain collision.

Abstract: An integrated circuit fabrication technique for a maskless method of forming contact regions in integrated circuits is disclosed. By carefully controlling implant dosages, ions of one conductivity type can be introduced into substrate regions having the same conductivity type to form enhanced characteristic contact regions without affecting the operational characteristics of substrate regions having the opposite conductivity type. The resulting cross-sectional profile of the regions of the one conductivity type allows fabrication overlap tolerances to be reduced and improves the contact regions' imperviousness to the spiking phenomenon.

Abstract: Apparatus and associated methods are disclosed for converting serial data pattern signals, transmitted or suitable for transmission over a high speed synchronous serial transmission media, to parallel data pattern output signals. The disclosed devices are modular, may each be packaged as a single semiconductor integrated circuit device and are cascadable. When cascaded, the devices are capable of generating parallel data pattern output signals to one or more data sinks from a single serial bit stream.

Abstract: A highly planarized integrated circuit structure having at least one bipolar device and at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with portions defined therein respectively for formation of a collector region and a base/emitter region for a bipolar device and a source/gate/drain region for an MOS device. All of the contacts of the devices are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.

Abstract: An improved contact construction for an integrated circuit structure having closely spaced electrodes adjacent the contact is disclosed. The integrated circuit structure having the improved contact comprises a substrate having an insulating layer thereon, a first conductive layer over the insulating layer, and a second insulating layer formed over the first conductive layer. A self-aligned contact opening is formed through the second insulating layer, the underlying first conductive layer, and the first insulating layer to expose the substrate. A layer of insulating material is then formed on the sidewalls of the opening to cover the exposed edges of the first conductive layer. Conductive material is then placed in the self-aligned contact opening and a second conductive layer is formed over the second insulating layer whereby the conductive material placed in the self-aligned contact opening electrically connects the substrate with the second conducting layer.

Abstract: A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal which determines the counting by one or two. The increment/decrement section is responsive to count signal and an increment strobe signal for generating an incremented output signal and a decremented output signal. The carry section is responsive to the increment/decrement section and the input carry signals for generating a carryout-by-one signal and a carryout-by-two signal. A number of these counter cells are arrayed to form an N-bit counter.

Abstract: An improved, high-speed frequency divider circuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of operation. The design of the frequency divider circuit (32) embodies a sagacious state assignment to minimize the number of bits that change state on any given state transition, thus reducing the possibility of faulty circuit operation.

Abstract: A code conversion system is described for converting a stream of data between first and second data codes. The stream of data containing data packets is recognized to be subject to a data fault condition arising from the collision of data packets. The conversion system comprises means for detecting the fault condition, and means for altering the code conversion of the stream of data between the first and second codes so as to reflect the occurrence of the fault condition in the code converted stream of data.

Abstract: A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state.

Abstract: An incrementer cell includes an input section, an output section and a carry section. The input section is responsive to an input data signal and an input carry signal for generating an incremented output signal. The output section is coupled to the input section for generating a data out signal to be either the incremented output signal or the input data signal. The carry section is responsive to the input data signal and the input carry signal for generating a carry-out signal.

Abstract: There is disclosed herein a servo data demodulator for use in magnetic head positioning servo system for disk drives. The demodulator is comprised of a single peak detector which detects the maximum amplitude of the peaks in an input signal during specific times. A storage capacitor is used in the peak detector to store the peak level. This peak level is sampled a predetermined number of times during each data frame. Each sample is taken by a different sample and hold circuit, and the sequence of the samples is controlled by a timing generator. The capacitor of the peak detector is discharged by a switch controlled by the timing generator after each sample and before the next sample. The time delay before the first sample from the start of the frame and the sample time in the sequence is programmable by the user by setting certain inputs into the timing generator.