Abstract: An unloading mechanism for unloading automatically a box, includes an endless conveyor belt with a conveyor beld extension for transporting a box to be unloaded. A cage device is used to receive the box to be unloaded from the conveyor belt. Air cylinder actuators are operatively connected to the belt extension for pivoting downwardly the belt extension in order to permit rotation of the cage device. Rotary air cylinders are operatively connected to the cage device for rotating the cage device through approximately 165.degree. in a first direction in order to unload the contents of the box into a hopper.

Abstract: A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements." Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control.

Abstract: A high access speed memory for the internal storage of data and the addressable input/output transfer of data thereto, the memory comprising means for the dynamic storage of data, means for the static storage of data, and means for transferring data between the dynamic storage means and the static storage means. The intimate interfacing of the static and dynamic memories provides a high access speed pathway to the dynamically stored data while impacting minimally on sense amplification timing and the use of a redundant dynamic memory scheme.

Abstract: A hysteresis circuit is disclosed in which a first signal path, including a hysteresis feedback loop, is separate from a second signal path that is used to carry data. When the signal input to the hysteresis circuit (also referred to hereinafter as the "input signal") crosses a first preselected hysteresis reference of ("threshold") level, the hysteresis feedback loop, which includes threshold adjustment means, will cause a change in the threshold from the first preselected level to a second preselected level. This adjustment of threshold level will take place in parallel with the data being propagated to the output over said separate second signal path. A subsequent crossing of the second preselected threshold level by said input signal will cause the first threshold level to the reset and so on.

Abstract: A static PLA circuit includes a logic gate portion, a precharge circuit portion and a feedback circuit portion. The feedback circuit portion is connected between the output of the logic gate portion and the input of the precharge circuit portion. The feedback circuit portion functions to delay the turn-on time of the precharge circuit portion when the output of the logic gate portion is making a high-to-low transition, thereby increasing the speed of the output transition.

Abstract: The invention discloses an improved PC board package for at least one integrated circuit die utilizing a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The cavity walls are plated to seal off portions of the PC board exposed by formation of the cavity to thereby prevent subsequent outgassing. Heat tubes are formed in a PC board adjacent the PC board with the cavity to conduct heat from an integrated circuit chip mounted in the cavity to an opposite surface of the package.

Abstract: An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: Current switches are used to control current into the columns during READ operations of a PROM. The circuit provides one such switch for each of the columns of the PROM and makes possible the use of a single current source which is connected to each of the switches but supplies current only to the column of the PROM that is currently selected for reading. A high voltage pre-bias is applied to the collectors of the NPN transistors used as current switches such that turn-on speed is improved because the collector parasitic capacitances are pre-charged to near the supply potential.

Abstract: A single, programmable, multifunctional input circuit scheme for integrated circuit chips is disclosed. An input pin is provided with selectable input logic circuit blocks, each capable of providing an input signal to another circuit in the integrated circuit system architecture. The user of the chip is provided with means for programming said pin to select one of said logic circuit blocks, whereby each said pin has multifunction capability.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: A single-chip microprogram sequence controller can be selectively operated in either an interrupt mode or a trapped mode. In the interrupt mode, the miroprogram sequencer allows the currently-executing microinstruction to finish execution before beginning the interrupt routine which services the asynchronous event which requested the interruption of the presently-executing microinstruction stream. In the trap mode, the sequencer aborts the currently-executing microinstruction to avoid an irreversible error which would result if the microinstruction were to finish execution before beginning the routine which services the event which requested trapping of the presently-executing microinstruction.

Abstract: A programmable event generator for generating digital timing waveforms in response to a triggering signal includes one programmable read-only memory for storing and outputting data words corresponding to the digital timing waveforms and next address words to address another of the data words, a storage register for temporarily storing and outputting any one of the data words and next address words, another mapping programmable read-only memory for storing and outputting starting address words to start the addressing of the one programmable read only memory, a multiplexer to select either a starting address word or a next address word to address the one programmable read-only memory, and a programmable control circuit, responsive to the triggering signal, for clocking the storage register at a programmed clock frequency.

Abstract: A D-type master-slave flip-flop includes a master section, a slave section and an output state protection network. The master section has a data input node and a clock input node. The slave section has at least one data output node connected to an output terminal. The output state protection network is responsive to the master section for toggling the slave section so that the data output node is returned to its initial logic state when the output terminal is free of transient noise.

Abstract: A protective housing for a leadless chip carrier or plastic leaded chip carrier package includes a substantially rectangular-shaped solid body having a central cavity for receiving a chip package. The solid body is formed of four side portions. Beam members are pivotally connected on opposite sides of two of the four side portions of the solid body for retaining the package within the central cavity. A plurality of support members are formed on the interior surface of the two opposite side portions and the beam members for supporting the lower surface of the package at each of its four corners. The solid body is provided with two opposite chamfered corners for moving outwardly the beam members away from the central cavity so as to permit insertion or removal of the chip package from the central cavity.

Abstract: An integrated circuit package having a plurality of pins and a plurality of output structures connected, respectively, to the plurality of pins. Each output structure selectively provides any one of four signals including a registered signal, non-inverted or inverted, or a non-registered signal, non-inverted or inverted, to a pin. Each output structure is configurable or field-programmable by a user or purchaser of the package to provide it with any desired combination of registered and non-registered outputs.

Abstract: Methods are disclosed for operating receiver devices which take serial data patterns off a high speed synchronous serial transmission media and covert the data to parallel pattern outputs. According to the invention, each device operates under a "permission to capture" data protocol which allows a given receiver to operate at the byte rate of the transmitted data. Devices using the disclosed methods may be operated individually or in a cascaded fashion, In either mode, by enabling the receivers to transfer high speed data at the transmitted pattern byte rate, as opposed to the bit rate, the reliability and capacity of the receivers to field high speed data is enhanced. In addition, the disclosed methods obviate the need for receivers operating in a cascade mode to "know" their position in a cascade chain. As a result the operating simplicity and reliability of devices that employ the disclosed methods is further enhanced.

Abstract: An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications.

Abstract: An operational amplifier suitable for inclusion in an integrated circuit device operating as a transceiver at a coaxial media interface to a network meeting IEEE 802.3 standards. To be included in an integrated circuit package the operational amplifier must have low-power consumption and yet generate up to 80 mA of current onto the network. A design method achieves this goal, producing an operational amplifier having three independently-positioned, isolated, poles. A current generator and level shifter is employed with the operational amplifier which generates a current precisely proportional to a "collision" reference voltage, the current is compensated for changes in temperature and for variations in transistor gain (hFE). A very wide band level shifter matches the current generated to the requirements of the operational amplifier so that 10% to 90% changes in current generated by the op amp can occur in 1/2 to 3/4 of a nanosecond, yet the level shifter does not consume much power.