Abstract: An improved method of making a bipolar transistor is disclosed which comprises forming one or more mask layers over a silicon substrate, etching at least one of said one or more masking layers to define a base contact area and a spaced apart collector contact area with an unetched emitter contact area defined in-between, forming a collector slot in a substrate of an integrated circuit structure through the collector contact area defined in the one or more mask layers, oxidizing the sidewall of the collector slot, filling the collector slot and the base and collector contact regions with polysilicon, removing one or more of the mask layers between the polysilicon base and collector contacts, oxidizing the exposed sidewalls of the polysilicon base and collector contacts, forming an emitter contact region between said collector and base contact regions insulated from the base and collector contacts by the sidewall oxidation thereon, and forming a base region in said substrate spaced from the collector slot by th

Abstract: The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region.

Abstract: A decoder/multiplexer circuit for selecting one of a plurality of input signals includes an array formed of a plurality of decode transistors. All of the collectors of the decode transistors are commonly formed in a large epitaxial pocket, thereby reducing the amount of chip area required.

Abstract: The substrate active region contains the source and drain regions for the transistors in each cell. The grounded drains of the two pulldown transistors extend symmetrically into the three adjacent cells coupling with six other pulldown drains. This common ground node has a single upward contact to the metal ground lead. The poly-2 has a similar voltage node coupling eight pulldown resistors in four adjacent cells to the metal Vdd lead. The poly-2 forming the lightly doped resistor area has a heavily doped conductive area at each end for coupling the resistor into the pulldown circuit. The pulldown gate bands have 45 degree bends to maximize the gate area relative to the pass gate area. The gate bends cooperate with corresponding 45 degree slants in the edges of the active region to minimize the effect of misalignment. A conductive poly word line forms the pass gates just above the active region.

Abstract: A single component electrically erasable memory cell is disclosed. A floating gate MOSFET having a relatively short channel is triggered into a snap-back mode positive feedback biasing mechanism. Hot-hole injection onto the floating gate during the snap-back mode neutralizes any charge stored there to represent a data bit.

Abstract: An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device further comprising: at least two respective ports for receiving respective combinations of binary address signals corresponding to respective locations of said memory array; transition detection and signal providing circuitry for detecting a change in a respective binary address signal combination received by either a first or second of the at least two ports and for providing a first transition signal in response to a change in a respective first combination of binary address signals received by the first port and for providing a second respective transition signal in response to a change in a respective second combination of binary address signals received by the second port; and contention detection and signal providing means for receiving the first and the sec

Abstract: A CMOS address transition detector includes a first input circuit section, a first delay circuit section, a second input circuit section, a second delay circuit section and an output circuit section. The first input circuit section and the first delay circuit section are responsive to true address transition signals for controlling the pulse width of an output pulse signal. The second input circuit section and the second delay circuit section are responsive to a false address transition signal for controlling the pulse width of the output signal. The output circuit section generates at an output terminal the output pulse signal having a pulse width which is substantially constant over a wide temperature range. The output circuit section has a first input which is responsive to the first input circuit section and the first delay circuit section when the true address transition signal makes a low-to-high transition.

Abstract: An integrated circuit having multiple programmable arrays in which a first programmable array receives a plurality of first inputs and generates a plurality of first outputs as programmed by the user. Also, a second programmable array receives a plurality of second inputs and generates a plurality of second outputs as programmed by the user. Also, buried state registers store signals as programmed by the user. An input multiplexer selects and supplies the first and second inputs from a variety of sources, including the first and second outputs, the buried state registers and I/O pins. An output multiplexer selects and supplies output signals to a set of output pins from a variety of sources, including the first and second outputs and the buried state registers.

Abstract: An adjustable sense amplifier circuit for read/write control of solid state memory devices is described. In a write mode the circuit includes a write select path, coupled to a current source and coupled to a differential pair of data select transistors, wherein the input data state sets each of two differential pairs formed by the memory element cross-coupled latch, such that the memory element stores selected data. In a sense mode, a second current path is selected wherein an adjustable sense level is provided to each of two differential pairs formed by the memory element. The current source is coupled to a reference voltage source which is independent of the supply voltage. The reference voltage source tracks changes in temperature and also provides low beta compensation for current loss due to the low beta value of transistors in the write and sense paths.

Abstract: A tag buffer having built-in testing capabilities is disclosed. In a single-chip, integrated-circuit design which includes a SRAM, a parity generator and checker, and a comparator, a method and capability of testing the functionality of the SRAM and parity components is defined. For an embodiment in which the SRAM component includes a redundancy scheme for replacing a defective memory array row, a test for determining whether a redundant row has been used is also provided.

Abstract: There is disclosed herein a servo data decoder which can decode both quadrature and non quadrature servo data. The decoder is comprised of a servo data amplitude demodulator to generate position error signals and a position error signal processor to generate a GPES signal to serve as a position error signal during the track following mode and a velocity signal and a track crossing signal for use in the seek mode. The user system may have either single or double pulse sync, and double pulse sync spacing, pulse window time and sync to first data pulse delay are user definable. The user may adjust the gain of the system in two manners and may program the frequency response characteristics of the phase locked loop. Many other user definable or user alterable features are provided.

Abstract: Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

Abstract: Three-level ECL or four-level CML are feasible when a low drop current source is incorporated in the series-gated arrangement. The low drop current source consumes less than one-tenth of the voltage span between V.sub.CC and ground. A greater portion of the voltage span between V.sub.CC and ground, up to 4 volts, is therefore reserved for the three ECL levels or four CML levels of logic. Conventional power supplies are utilized yet the number of logic functions is increased.

Abstract: An improved integrated circuit structure is disclosed which comprises a Vcc bus and a Vss bus having capacitance means coupled between the busses and distributed along the length of the busses to reduce the voltage spikes induced during switching. In a preferred embodiment, the capacitance means comprise one or more capacitors formed beneath one of the busses. Construction of MOS capacitors beneath one or more of the busses is disclosed.

Abstract: A multiplexer for use in a digital subscriber controller having a number of analog ports and digital ports which can be programmed via an external microprocessor to establish time-division multiplexed bidirectional data paths between three subscriber-selected ports designated as "sources" and three subscriber-selected ports designated as "destinations". Among the ports is a line-interface port having two 64 kilobit-per-second channels on which analog/digital data is received from and transmitted onto the network transmission line. Among the digital ports is a three-channel serial port and a two-channel microprocessor interface port. An analog port is also provided at which a variety of audio transducers may be connected.

Abstract: A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location.

Abstract: Method and apparatus suitable for inclusion in an integrated circuit transceiver meeting IEEE 802.3 standards which detects "collisions" so that more than one station will not simultaneously transmit over a network. The method employs a novel three-pole cyclical low-pass filter which attenuates the ac component received over the network to less than 20 mV to allow collision detection within the 900 nanosecond budget allowed by the IEEE standard. A differential operational amplifier receives the signal from the network and a collision reference voltage. The signal generated by the differential amplifier is filtered by the low-pass filter and then coupled to a high-gain comparator which acts as a zero-crossing detector. The comparator generates ECL logic signals representing the occurrence or non-occurrence of a collision. The resulting collision detector operates over a wide range without the need for field "trimming".

Abstract: An integrated circuit device for protecting the circuitry of an integrated circuit from an electrostatic discharge into an output pin of the chip is disclosed. In a preferred embodiment, the device comprises an n-well, n-channel, polysilicon-gated FET structure, which operates in a punch-through mode, coupled to an output pad and an output buffer of the circuit. Back biasing in the chip system affords additional inhibition to turn-on during normal system operation.

Abstract: A bias generator for use in CML gate circuits provides an output reference voltage that is substantially independent of variations in supply voltage over a wide temperature range. The bias generator includes a temperature and voltage compensating circuit portion which is formed of an emitter resistor and a diode-connected transistor. The emitter resistor is used to control the output reference voltage for the lower temperatures and the base-emitter voltage of the transistor determines the output reference voltage for the higher temperatures.

Abstract: A bipolar transistor susceptible to high level integration has its active regions formed in slots within a semiconductor substrate. In one embodiment, the emitter is formed within a slot and has a surrounding region doped to function as a base. A collector is formed in another slot which is located adjacent but spaced apart from the emitter slot. Carrier transport occurs principally horizontally between the emitter and base and then to the collector. Additional slots may be used to isolate the slot transistor in conjunction with a horizontally disposed pn junction and a buried collector. The collector may be formed in a slot which contains an oxidized outer sidewall that serves to isolate the individual transistor.