Patents Represented by Attorney, Agent or Law Firm Patrick T. King
  • Global reset and zero detection for a memory system
    Patent number: 5067110
    Abstract: A tag bit is provided for each row of a memory array. The tag bit is zero is all of the bits in a row are zeros. A detector scans input data to test for all zeros and the tag bit is reset to zero. The output signals for a row are forced to zero when the tag bit for that row is zero.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: November 19, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Thomas J. Runaldue
  • Multiport memory collision/detection circuitry
    Patent number: 5062081
    Abstract: A multiport memory system is provided with a collision detection system to prevent collision between information which is simultaneously being read to a particular memory row and information being written to that same memory row simultaneously. Memory rows of the multiport memory system are independently addressed by address signals for a first port and by address signals corresponding to a second port. Row select signals are generated from the address signals of each of the ports when the row select signals for one particular memory row of the memory array are simultaneously present a match signal is generated. The match signal controls a forwarding logic circuit which connects the write port information directly to the read port when a match is present, providing immediate access to the most current information being written into the memory array.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: October 29, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Thomas J. Runaldue
  • Integrated circuit structure with active device in merged slot and method of making same
    Patent number: 4803176
    Abstract: An improved integrated circuit structure is disclosed in which an active device is formed in contiguous portions of a single slot in an integrated circuit structure or substrate. The method of forming the single slot or merged slot device comprises forming a first portion of the slot, constructing at least a part of one element of the active device in this slot portion, and then forming one or more additional slot portions contiguous with the first slot portion, and constructing one or more further elements of the same active device in the additional contiguous slot portion or portions.
    Type: Grant
    Filed: August 18, 1986
    Date of Patent: February 7, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Robert W. Bower
  • Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
    Patent number: 4782380
    Abstract: Construction of a novel multilayer conductive interconnection for an integrated circuit having more than one conductive layer is disclosed comprising a lower barrier layer which may be in contact with an underlying silicon substrate and comprising a material selected from the class consisting of TiW and TiN; an intermediate layer of conductive metal such as an aluminum base metal; and an upper barrier layer which may be in contact with a second aluminum base metal layer and which is selected from the class consisting of TiW, TiN, MoSi.sub.x and TaSi where x equals 2 or more.
    Type: Grant
    Filed: January 22, 1987
    Date of Patent: November 1, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishna Shankar, Ram Ramani
  • High density, dynamic, content-addressable memory cell
    Patent number: 4780845
    Abstract: A content-addressable memory cell and memory array are disclosed. Each cell comprises a random access memory storage component and a comparison component for performing the contact addressability function. In a disclosed CMOS embodiment, a DRAM cell and an exclusive-NOR gate are combined to form the CAM cell.
    Type: Grant
    Filed: July 23, 1986
    Date of Patent: October 25, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: N. Bruce Threewitt
  • Writing speed in multi-port static rams
    Patent number: 4764899
    Abstract: A write-bias gate in the form of an FET is provided for each of the bit-lines. Each FET has its drain electrode connected to logic 1 and its source electrode connected to the bit-line. When one port is writing, the write-bias gates on the other port(s) are driven by a signal which causes them to enter a pass condition, supplying extra current to pull up the bit lines of the non-writing port(s).
    Type: Grant
    Filed: February 7, 1986
    Date of Patent: August 16, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kent D. Lewallen, Steven J. Schumann
  • Carry-bypass arithmetic logic unit
    Patent number: 4764887
    Abstract: An arithmetic logic circuit comprising a plurality of cells of conventional logic circuits for performing logical and arithmetic operations in combination with a kill circuit in each one of the cells which is responsive to bits of first and second operands T and B, a clock signal .0.1*, a propagate bit P and a carry-in bit C.sub.in for selectively providing a carry-out bit C.sub.out and/or a carry-bypass circuit coupled to each one of a plurality of sets of cells which is responsive to propagate bits P from said cells in each set, a clock signal .0.2* and a carry-in bit C.sub.in for allowing said carry-in bit C.sub.in to bypass selected ones of the cells.
    Type: Grant
    Filed: August 2, 1985
    Date of Patent: August 16, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chingwei S. Lai, Florence S. Lee
  • Digital receive filter circuit
    Patent number: 4764923
    Abstract: A digital filter receive circuit for use with a StarLAN coded data transceiver includes three D-type flip-flops and four NAND logic gates. The digital receive line filter circuit is capable of being implemented as part of a single monolithic integrated circuit containing the transceiver, thereby producing a miniaturized and compact structure.
    Type: Grant
    Filed: March 3, 1987
    Date of Patent: August 16, 1988
    Assignee: Advance Micro Devices, Inc.
    Inventors: Leslie Forth, Raymond S. Duley
  • Nitride-less process for VLSI circuit device isolation
    Patent number: 4762805
    Abstract: An integrated circuit fabrication technique for constructing field isolation structure components and subposing electrical barrier isolation region components in a substrate is disclosed. A nitride-less mask is used to pattern a major surface of the substrate with apertures where the isolation barrier components are to be implanted. Following the formation of the isolation components, a thick oxide is formed on the substrate, masked, and etched to form field oxide structures on the major surface of the substrate. Bird beaks, bird crests, crystalline dislocations and white ribbon problems associated with nitride masking processes are virtually eliminated.
    Type: Grant
    Filed: December 17, 1985
    Date of Patent: August 9, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robin W. Cheung, Hugo W. K. Chan
  • Clock scheme for VLSI systems
    Patent number: 4761567
    Abstract: An integrated circuit includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit responsive to either the internal CMOS level system clock signal or an external CMOS level system clock signal for generating internal CMOS level phase clock signals for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.
    Type: Grant
    Filed: May 20, 1987
    Date of Patent: August 2, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Donald M. Walters, Jr., Gigy Baror
  • Bounds checker
    Patent number: 4760374
    Abstract: A bounds checker consisting of a pair of comparators that each compare a 16-bit number with a lower and an upper limit stored in registers. The device is preferably constructed as a single integrated circuit chip employing emitter coupled logic (ECL) circuitry and can be made externally compatible with either transistor transistor logic (TTL) circuitry or ECL circuitry. The device can be cascaded to operate on extended-precision numbers and has a pin which can be used to select comparison of numbers either as signed two's complement numbers or as unsigned numbers. No added gate delay is imposed by the device's ability to operate either type of number.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: July 26, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ole H. Moller
  • Quasi content addressable memory
    Patent number: 4758982
    Abstract: A quasi content addressable memory circuit including a CAM section, a RAM section, and a comparator. A first part of an incoming comparand is applied to the CAM section, while a second part of the incoming comparand is applied to the comparator. If there is a favorable comparison within the CAM section with the first part of the comparand, the CAM section develops a pointer which addresses the RAM. The output of the RAM is then compared to the second part of the comparand and, if a favorable comparison is made, a match flag is developed. Also disclosed are circuits for handling multiple responses by the CAM section, and a practical comparator RAM which combines the functions of the comparator and the RAM of the quasi content addressable memory circuit.
    Type: Grant
    Filed: January 8, 1986
    Date of Patent: July 19, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Simon M. Price
  • Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor
    Patent number: 4758747
    Abstract: A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or an output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.
    Type: Grant
    Filed: May 30, 1986
    Date of Patent: July 19, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michele Young, Kapil Shankar
  • Switching plane redundancy
    Patent number: 4754434
    Abstract: A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.
    Type: Grant
    Filed: August 28, 1985
    Date of Patent: June 28, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Moon-Yee Wang, James Yu, Hong-Gee Fang
  • Single-chip programmable controller
    Patent number: 4754393
    Abstract: A single-chip microprogrammable sequence controller includes a subroutine stack and conditional branching facilities. The controller performs a test and mask operation followed by comparison with a user-defined constant to effect a Boolean sum-of-product function. Address control logic includes a flag signal set by compare logic; the flag is available to a microinstruction decoder where it can be used during a subsequent conditional branch operation based on the setting of the flag.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: June 28, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bradford S. Kitson, Warren K. Miller
  • ECL circuit with output transistor auxiliary biasing circuit
    Patent number: 4751406
    Abstract: An ECL circuit comprising an output transistor having a base, a resistor coupled to the base, a first circuit responsive to a deselect signal OE for drawing a first current through the resistor and a second circuit responsive to the deselect signal OE for drawing a second current through the resistor, said first and said second currents combining in said resistor for providing a predetermined turn-off bias potential on said base of said output transistor. The predetermined turn-off bias potential reduces the emitter current of the output transistor such that the noise immunity of a data bus is preserved when a plurality of output transistors are coupled in parallel to the data bus.
    Type: Grant
    Filed: May 3, 1985
    Date of Patent: June 14, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Stanley Wilson
  • Vertical slot bottom bipolar transistor structure
    Patent number: 4749661
    Abstract: An improved bipolar slot transistor vertically formed in a slot in an integrated circuit structure is disclosed. The transistor is formed in a substantially vertical slot having an active base region formed beneath the bottom of the slot and comprises an active collector region formed beneath the active base region, a buried collector layer beneath the active collector region and in communication with a collector contact; an emitter region formed in the slot over the active base region; and extrinsic base regions formed adjacent to but insulated from the sidewalls of the slot communicating with the active base region and with base contact regions on the surface of the structure.
    Type: Grant
    Filed: August 18, 1986
    Date of Patent: June 7, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Robert W. Bower
  • Parallel multiplier array with foreshortened sign extension
    Patent number: 4748582
    Abstract: A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.
    Type: Grant
    Filed: June 19, 1985
    Date of Patent: May 31, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bernard J. New, Timothy J. Flaherty
  • Multi-precision fixed/floating-point processor
    Patent number: 4748580
    Abstract: A single-chip fixed/floating-point arithmetic processor, a three port ALU, a plurality of storage registers R, S, F0 and F1, a constant store circuit and an output data register F. Two of the storage registers R and S are provided for storing 64-bit input operands and two of the regusters F0 and F1 are provided for storing 64-bit results of operations performed in the ALU. Each of the registers are provided with three output ports and corresponding pass gates for selectively transferring data from the registers to the three inputs of the ALU under the control of control signals applied to the pass gates. The constant store is also coupled to one of the input ports of the ALU by a pass gate for transferring constants to the ALU under the control of a pass gate. Results of the ALU are provided to the data output register F for further processing off-chip.
    Type: Grant
    Filed: August 30, 1985
    Date of Patent: May 31, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Charles D. Ashton, David K. Quong, Alan G. Corry
  • Temperature compensation for ECL circuits
    Patent number: 4745304
    Abstract: An ECL circuit comprising an output transistor having a high output voltage VOH guard band and a low output voltage VOL guard band with a temperature compensating network coupled to the output transistor for causing the high level output voltage VOH and low level output voltage VOL of the output transistor to remain within the maximum and minimum limits of the VOH and VOL guard bands over a wide temperature range.
    Type: Grant
    Filed: May 3, 1985
    Date of Patent: May 17, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Stanley Wilson