Abstract: Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material (76) following the source/drain implant (74).

Abstract: The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator.

Abstract: Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layer 226 of FIG. 2a) on the first conductor (conductor 222 of FIG. 2a), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layer 234 of FIG.

Abstract: The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention, includes patterning an opening 220 in a photoresist layer 210 located over an intermediate layer located over a substrate. In that particular embodiment the opening 220 has a predetermined width 230. The method may further include etching into the intermediate layer 120 such that an intermediate opening 310 is formed, the intermediate opening 310 having a decreasing width that terminates at a targeted width 320 less than the predetermined width 230. Additionally, the method may include continuing the etching within the intermediate opening 310 and at least partially into the substrate 110 to form a via opening 510 in the substrate. In this particular embodiment, the width 520 of the via opening 510 is substantially equal to the targeted width 320.

Abstract: The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective agent (120) to form a protective layer (125). The method also includes placing the semiconductor substrate in an acid bath (145) to remove the protective layer. The method further includes electrochemically depositing a second copper layer (155) on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the n-type substrate (125). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

Abstract: A system and method for a plunger assembly includes a tuning slug with a bore in the stem, a tuning screw rotatably disposed in the stem, and a coupling assembly to rotatably secure the tuning screw to the slug. The system and method may also include a locking assembly to secure the postion of the assembly.

Abstract: A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).

Abstract: A static logic circuit with a pull-up network (155) and a pull-down network (160). The network is fabricated on SOI substrates and the pull-up network comprises at least one NMOS transistor (115) and the pull down network comprises at least one PMOS transistor (120).

Abstract: In one embodiment, a system for custom-polarized photolithography illumination includes an illuminator operable to generate an illumination pattern of light, a polarizer unit operable to variably polarize the light, and a mask pattern defining photolithographic pattern features in two dimensions. The mask pattern is associated with a mask capable of transmitting at least a portion of the variably polarized light through the mask pattern.

Abstract: A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer (38) adjacent at least a portion of the upper surface, and a polysilicon layer (16) adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer (201) positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer (202) adjacent the first conductive layer, and a second conductive layer (203) adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.

Abstract: The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

Abstract: The present invention provides, in one aspect, a method of testing an electrical breakdown characteristic of a dielectric in a microelectronic device. This method includes determining a first dielectric breakdown voltage distribution of a first test sample by using a first voltage ramp rate, determining a second dielectric breakdown voltage distribution of a second test sample by using a second voltage ramp rate and determining a spacing distribution between conductive lines in the first and second test samples based on a field acceleration factor associated with the dielectrics of the first and second test samples, the first and second voltage ramp rates, and a difference between the first and second breakdown voltage distributions. This spacing distribution is used to determine corrected electric breakdown fields based on a measured breakdown voltage of a test sample, to improve microelectronic-device screening for interconnect dielectric reliability.

Abstract: Photo reticles (110) are formed comprising a first and second printable features (130), (140) which are connected by a channel assist feature (150). The size of the channel assist feature is such that the channel assist feature will not substantially print on photoresist that is exposed using the reticle. Third printable features (120) can be placed a distance WD from the channel assist feature (150). The channel assist feature will assist in the formation of the third printable feature (120).

Abstract: A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.

Abstract: In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.