Patents Represented by Attorney, Agent or Law Firm Plotkin & Kahn PLLC
  • Patent number: 6404688
    Abstract: A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: June 11, 2002
    Assignee: Fujitsu Limited
    Inventors: Yoshiaki Okuyama, Yoshitaka Takahashi, Shinya Fujioka, Akihiro Funyu
  • Patent number: 6405346
    Abstract: A design method optimizes the dimensions (length and width) of power supply lines in a semiconductor integrated circuit. First, the power supply lines are analyzed to determine initial values for the lines. Then, a current-capacitance ratio of each of the power supply lines is calculated using the analysis results. Finally, a dimension of each of the poser supply lines is computed so that the corresponding current-capacitance ratio is within a predetermined range. The resulting power supply lines are as narrow as possible without causing a voltage drop violation or a current amount violation.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: June 11, 2002
    Assignee: Fujitsu Limited
    Inventor: Takanori Nawa
  • Patent number: 6404644
    Abstract: A non-contact IC card (1, 2, 30, 50) includes a substrate (10), a coil (12, 32, 52, 57) provided on substrate (10), and an IC chip (11, 31, 51) electrically connected to a coil (12, 32, 52, 57) and having a main surface (11c, 31c, 51e). IC chip has a terminal (11a, 11b, 31a, 31b, 51a, 51b, 51c, 51d) formed in main surface (11c, 31c, 51e). Coil (12, 32, 52, 57) has a coil inner end (12b, 32b, 52b, 57b) electrically connected to a terminal (11b, 31b, 51b, 51d) and a coil outer end (12a, 32a, 52a, 57a) electrically connected to a terminal (11a, 31a, 51a, 57c). IC chip (11, 31, 51) is provided above coil (12, 32, 52, 57) such that coil inner end (12b, 32b, 52b, 57b) is positioned in vicinity of terminal (11b, 31b, 51b, 51d) and coil outer end (12a, 32a, 52a, 57a) is positioned in vicinity of terminal (11a, 31a, 51a, 51c).
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: June 11, 2002
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshihiro Ikefuji, Hiroharu Okada
  • Patent number: 6402661
    Abstract: An automatic gear change controller, having a constant speed travel mode, which can transmit torque to wheels of a vehicle according to changes in the travel load of the vehicle even though a gear shift mode is changed to the manual gear shift mode. When the gear shift mode is set in the manual gear shift mode and the travel mode is set in a constant speed travel mode, a constant speed travel controller generates a downshift command signal. In this case, when the accelerator pedal is depressed beyond a predetermined amount, the gear shift stage of the automatic transmission is downshifted.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: June 11, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Yukio Morita, Kazuyuki Konnno, Kenji Hagiwara, Takamichi Shimada
  • Patent number: 6404692
    Abstract: A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: June 11, 2002
    Assignee: Fujitsu Limited
    Inventors: Masato Takita, Yuichi Uzawa, Shinichi Yamada, Masato Matsumiya
  • Patent number: 6405062
    Abstract: A battery level indicator is provided in a mobile phone, which is equipped with a communication mode and a standby mode where the current drawn from the battery is different, to display the level of the battery that powers the mobile phone. The battery level indicator includes a battery voltage measuring unit, a correction unit, a level determining unit and a liquid crystal display. The battery voltage measuring unit measures the voltage of the battery at regular intervals, such as every 0.5 seconds. The correcting unit corrects voltage measurements obtained during communication mode by adding correction values specified using a correction value table. The level determining unit calculates an average for voltage measurements, which have been corrected as necessary, produced during a preceding period such as fifteen seconds. This average may be calculated every second, for example.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: June 11, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masahiro Izaki
  • Patent number: 6399054
    Abstract: A method for the production of activated tumor-specific T cells by co-cultivating, ex vivo, tumor cells from a patient with T cells from that patient, comprising the steps of: i) incubating the tumor cells with a first fusion protein obtained from a B7 protein and one partner of a biological binding pair and a second fusion protein obtained from an antibody against a cell surface antigen and the other partner of the biological binding pair, ii) inhibiting the proliferation of the tumor cells prior to or after that incubation; iii) co-cultivating the tumor cells with the T cells to be activated, until activation of the T cells is attained; iv) separating the activated T cells from the tumor cells, is highly efficient and can be carried out in a simple manner.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: June 4, 2002
    Assignee: Science Park RAF S.p.A.
    Inventors: Giulia Casorati, Paolo Dellabona
  • Patent number: 6400535
    Abstract: A MR multi-layered structure or a thin-film magnetic head with the MR multi-layered structure includes a non-magnetic electrically conductive material layer, first and second ferromagnetic material layer separated by the non-magnetic electrically conductive material layer, and an anti-ferromagnetic material layer formed adjacent to and in physical contact with one surface of the second ferromagnetic material layer, the one surface being in opposite side of the non-magnetic electrically conductive material layer. The second ferromagnetic material layer includes a first layer of a ferromagnetic material containing Co, and a second layer of a ferromagnetic material with a smaller magnetic anisotropy than that of Co.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: June 4, 2002
    Assignee: TDK Corporation
    Inventors: Koji Shimazawa, Tetsuro Sasaki, Manabu Ohta
  • Patent number: 6400615
    Abstract: A voltage raising circuit of a semiconductor memory includes a compensating circuit. The compensating circuit has a negative dependency on a source voltage for controlling a variation of a raised voltage caused by a variation of the source voltage, and a positive dependency on temperature for controlling a variation of the raised voltage caused by a variation of the temperature.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventor: Yuichi Einaga
  • Patent number: 6398292
    Abstract: In an automotive vehicle body structure including a crash load transmitting member extending from a front end of the vehicle body to a part adjacent to the floor member, and integrally carrying a seat thereon, a stopper is fixedly attached to the main frame, and adapted to abut a part of the crash load transmitting member upon a rearward movement of the crash load transmitting member by a prescribed distance. A guide member normally retains the crash load transmitting member firmly to the vehicle body main frame as a part of the vehicle body, but allows the crash load transmitting member to move rearward, and hit the stopper so that the desired deceleration time history may be achieved in the crash load transmitting member which is integral with the seat, and the deceleration of the vehicle occupant may be favorably controlled.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: June 4, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Makoto Tsuruta, Takahiro Kamei, Yasuki Motozawa, Kazuya Yoshida
  • Patent number: 6399304
    Abstract: Method for synthesizing or sequencing a nucleic acid molecule in a thermocycling reaction which initially comprises a nucleic acid molecule, a first primer, a second primer, a reaction buffer, a first thermostable enzyme e.g. a DNA polymerase, (optionally) a thermostable pyrophosphatase, deoxynucleotides or derivatives thereof and in case of a sequencing method a dideoxynucleotide or a derivative thereof and which is characterized in that the thermocycling reaction additionally contains a second thermostable enzyme e.g. a DNA polymerase which, in comparison to the said first thermostable enzyme, exhibits a different enzymatic activity as e.g. has a reduced ability to incorporate dideoxynucleotides as well as the use of the said method. At least one polymerase is initially inhibited whereby the inhibiting agent loses inhibitory ability at cycles of the thermocycling reaction.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: June 4, 2002
    Assignee: Roche Diagnostics GmbH
    Inventors: Christian Kilger, Michael Motz
  • Patent number: 6400081
    Abstract: To facilitate evaluation of the amount of a deviation in a column direction between a front substrate and a rear substrate upon assembly of a plasma display panel, thereby improving alignment accuracy between the front substrate and the rear substrate and performances of the resultant plasma display panel, there is provided a plasma display panel comprising partition 15 and position alignment-use ribs 20. The partition 15 is formed of vertical walls 15a extending in a column direction and horizontal walls 15b extending in a row direction on a rear glass substrate 13 so as to partition a discharge space S between a front glass substrate 10 and the rear glass substrate 13 in the row and column directions in accordance with unit luminous regions. The position alignment-use rib 20 is formed on the rear glass substrate, and is positioned in cell Ca which is positioned at the outside of the display region of the plasma display panel within spaces partitioned by the partition 15.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: June 4, 2002
    Assignee: Pioneer Corporation
    Inventors: Tetsuya Matsumoto, Takashi Nakano
  • Patent number: 6399333
    Abstract: A process for producing erythropoietin which is free of foreign animal proteins except for the proteins of the host cell, wherein DNA coding for EPO is expressed in a eukaryotic host cell and the host cell is cultured in a medium free of natural mammalian proteins. The erythropoietin is chromatographically purified using dye affinity chromatography, chromatography on hydroxyapatite, reversed phase chromatography, and anion exchange chromatography. The resulting preparation contains less than 100 ppm of proteins derived from the host cell, and less than 10 pg of host cell DNA per 83 &mgr;g erythropoietin.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: June 4, 2002
    Assignee: Roche Diagnostics GmbH
    Inventors: Josef Burg, Walter Schneider, Alexander Wrba, Werner Fürst, Karl-Heinz Sellinger
  • Patent number: 6400209
    Abstract: A switch circuit has an input terminal and an output terminal and when turned on, provides a voltage at its input terminal to its output terminal. A transistor is connected between the input and output terminals. A gate drive circuit is connected to the gate of the transistor and provides a gate drive signal to the gate. The gate drive circuit, in response to a first control signal, causes the gate drive signal to have one of a first voltage derived from an input voltage at the input terminal and a low potential voltage. A back gate drive circuit is connected to a back gate of the transistor and provides a back gate drive signal to the back gate. The back gate drive signal controls a voltage applied to the back gate of the transistor depending on whether the transistor is turned on or off. The switch circuit may be used to selectively supply battery power to a portable electronic device.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Matsuyama, Koichi Inatomi
  • Patent number: 6400618
    Abstract: A semiconductor memory device, comprising a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Nakamura, Yoshinori Okajima, Hiroyuki Sugamoto
  • Patent number: 6400616
    Abstract: A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Hideki Takauchi, Tsz-shing Cheung, Kohtaroh Gotoh
  • Patent number: 6400617
    Abstract: A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Tadao Aikawa, Takaaki Suzuki, Yasuharu Sato, Hiroyuki Kobayashi
  • Patent number: 6397539
    Abstract: To provide flooring for a building, more specifically, flooring washable at its installation place in a building. In the flooring for a building which has a plurality of floor panels laid in parallel to constitute a whole floor, an opening is formed on a floor surface between one floor panel and its adjacent floor panel. The flooring for a building according to the present invention is provided with a gutter portion that is arranged below the opening to receive a liquid dripping from the opening. The gutter portion is formed as an integral part of the one floor panel, and communicates with a drain pipe for draining the liquid in the gutter portion to the outside. The present invention thus provides washable flooring for a building which is easy to construct.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: June 4, 2002
    Assignee: Kimura Corporation
    Inventor: Motoyasu Kimura
  • Patent number: 6397554
    Abstract: The thermal insulation of buildings is realized by the diffused reflection of thermal radiation and the diffused reflection of the thermal transition of the air, from the internal and the external surfaces of the sublayers of the external masonry, the external roofs, the internal masonry and the internal ceilings of the buildings. Thermal insulation is also realized by a low emission of thermal radiation, with the diffused reflection of thermal radiation and the diffused reflection of thermal transition of air, from the internal surfaces of a parallel plane division having an enclosed layer of air, which is surfaces of a parallel plane division having an enclosed layer of air, which is constructed at the internal side of the sublayers of the external masonry and the external roof of the buildings. These surfaces are covered with a reflective insulating material, which can be colored with the addition of coloring pigments.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: June 4, 2002
    Inventor: Dimitrios Kotrotsios
  • Patent number: D458327
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: June 4, 2002
    Inventor: Kouichi Higashida