Abstract: The present invention is relate to watermark information embedding apparatus and method for the same, watermark information detecting apparatus and method for the same, and method of containing watermark document. A document image generator (101) generates a document image according to document data (105). A watermark image generator (102) generates a watermark image. The watermark information (106) is denoted with dot pattern, and the dot pattern within the outline of the watermark information are of special value. A synthesizer (103) overlaps document image generated from the document image generator (101) and the watermark image generated from the watermark image generator (102) so as to generate a containing watermark document image.
Abstract: A block intra prediction direction detection algorithm comprises acts of dividing a block, finding directions from edge assent rules, determining a main edge of the block, selecting prediction modes from the main edge, choosing base prediction modes and using all unique selected and base prediction modes in intra prediction. The algorithms comprise a 4×4 block intra prediction direction detection algorithm, a 16×16 luminance block intra prediction direction detection algorithm and an 8×8 chrominance block intra prediction direction detection algorithm.
Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.
Type:
Grant
Filed:
July 13, 2010
Date of Patent:
June 19, 2012
Assignee:
Electronics and Telecommunications Research Institute
Abstract: A method for detecting SECAM-L signals is disclosed. First, a SECAM-L signal is received and demodulated into a demodulation signal. Then high frequency components of the demodulation signal are filtered out and a low frequency signal, including many sync pulses and many data pulses, is obtained. Next, the low frequency signal is inversion into an inversion signal, having many inversion sync pulses and many inversion data pulses. Afterwards a voltage level of the inversion signal is detected continuously whether it is a lowest level. After that, the lowest level is determined whether belonging to the inversion sync pulses when the voltage level of the inversion signal is the lowest level, and a detection signal is outputted. When the lowest level belongs to the inversion sync pulses, a voltage level of the detection signal is high, and the demodulation signal is an inversion SECAM-L demodulation signal.
Abstract: The invention provides a key update system for a multihop network system including an authentication management device that manages keys using a hierarchical structure. That device constructs key information having a hierarchical structure in accordance with the structure of the multihop network. In addition, that device determines respective encryption keys for encrypting the keys based on the key information, and the communication terminals obtain the respective keys. In this system, that device includes a key tree management portion that constructs and manages the key information; an encryption portion that encrypts the keys using the keys included in the key information; and a transmission portion that transmits the encrypted keys. Each communication terminal includes a receiving portion that receives the encrypted keys; a key management portion that manages the keys that need to be held and stored by the given communication terminal; and a decryption portion that decrypts the encrypted keys.
Abstract: A power detection method applied to a peripheral apparatus is provided. The method includes the following steps. First, a power signal is received from a data communication interface. Next, it is determined that whether the power signal is able to drive a main function device of the peripheral apparatus. Then, according to the determination result, the power signal is selectively provided to the main function device to drive the main function device.
Abstract: A motion vector searching apparatus to which a reference image, an object image and weight parameters for the reference image are inputted and searches a motion vector based thereon is provides. The motion vector searching apparatus includes an inverse weighting section that generates an inverse weighted object image by performing, on the object image using the weight parameter, a weighting inverse from a weighting performed on the reference image using the weight parameter; an image comparing section that compares the generated inverse weighted object image with the reference image to obtain a comparison value indicating a degree of approximation between the two images; and a determination section that determines an optimum motion vector from the comparison value.
Abstract: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.
Abstract: Super-structured fiber Bragg gratings (SSFBGs) of s optical pulse time spreaders are provided with N unit FBGs disposed starting from an input/output end in the order of first to N-th unit FBGs, where s is a parameter less than or equal to a parameter N, a natural number. The unit FBGs are configured such that the reflectivities of the unit FBGs placed from one end to the center of the SSFBG formed in an optical fiber are monotonically increased, while the reflectivities of the unit FBGs placed from the center to the other end of the SSFBG are monotonically decreased. The chip pulses in a pulse train are given relative phases such that the relative phase of the first chip pulse is equal to zero, the relative phase of the second chip pulse is equal to a phase difference d1=2?{a+(n?1)/N}, . . . , and the relative phase of the N-th chip pulse is equal to (N?1)d1. The parameter a is any real number satisfying the condition of 0?a<1.
Abstract: A video processor includes a video filter and a calculation circuit. The video filter performs a low-pass filtering operation on first frame data to obtain brightness distribution data. The calculation circuit obtains difference data between the brightness distribution data and second frame data. The calculation circuit multiplies the difference data and a weighting parameter together to obtain a product, and then summates the product and the second frame data together to generate processed frame data.
Abstract: A developer storing container includes outer and inner cases. The outer case includes first and second hollow portions. The first hollow portion includes a surrounding wall so shaped as to surround a center axis. The surrounding wall has both ends in a cross-section perpendicular to the center axis, and has an ejection opening. The second hollow portion includes first and second outer walls extending from both ends of the surrounding wall and a third outer wall disposed therebetween. The inner case is rotatably disposed in the first hollow portion, and has an opening corresponding to the ejection opening. The surrounding wall extends from one of both ends to the other of both ends at an angle greater than or equal to 180 degrees with respect to the center axis. An entire outer surface of the surrounding wall constitutes a part of an outer surface of the outer case.
Abstract: Provided is a method for manufacturing a semiconductor device. The method includes: providing a first substrate where an active layer is formed on a buried insulation layer; forming a gate insulation layer on the active layer; forming a gate electrode on the gate insulation layer; forming a source/drain region on the active layer at both sides of the gate electrode; exposing the buried insulation layer around a thin film transistor (TFT) including the gate electrode and the source/drain region; forming an under cut at the bottom of the TFT by partially removing the buried insulation layer; and transferring the TFT on a second substrate.
Type:
Grant
Filed:
April 26, 2010
Date of Patent:
June 12, 2012
Assignee:
Electronics and Telecommunications Research Institute
Inventors:
Jae Bon Koo, Seung Youl Kang, In-Kyu You
Abstract: A method of manufacturing a semiconductor light emitting device employs a substrate formed by successively stacking an n-type semiconductor layered portion including an AlGaN layer, a light emitting layer containing In and a p-type semiconductor layered portion on a group III nitride semiconductor substrate having a larger lattice constant than AlGaN. This method includes the steps of selectively etching the substrate from the side of the p-type semiconductor layered portion along a cutting line to expose the AlGaN layer along the cutting line, forming a division guide groove along the cutting line on the exposed AlGaN layer, and dividing the substrate along the division guide groove.
Abstract: Disclosed is a method of manufacturing a semiconductor device that does not have a defect, such as wire breakage, due to an uplifted portion created at a rewiring pattern in a multilayer wire structure. Before a wiring layer is formed on an insulation layer, the insulation layer is exposed via a mask. The mask has a weak exposure part and a strong exposure part. The mask is positioned such that the weak exposure part corresponds to an arrangement position of a wire line of an underlying wiring layer, and such that the strong exposure part corresponds to an arrangement position of a via part of the underlying wiring layer. The underlying wiring layer is a layer immediately below the insulation layer.
Abstract: A manufacturing method of an electric contact and manufacturing equipment of the electric contact. A contact and a metal base are superimposed and support by a jig, and a rotational tool, which rotates at a predetermined speed and advances/retracts to/from the jig, is pressed into a surface, which is not contacted with the contact, of the metal base while being rotated, so that the contact and the metal base are joined by solid state diffusion welding by using frictional heat generated by friction between the rotational tool and the metal base, and then the rotational tool is retracted from the metal base.
Type:
Grant
Filed:
January 16, 2009
Date of Patent:
June 12, 2012
Assignee:
Fuji Electric Fa Components & Systems, Ltd.
Abstract: A high voltage gain power converter includes: a main switch element; an assistant switch element; a first inductive element, a first switch element, and a first capacitive element; and a second inductive element, a second switch element, and a second capacitive element. The first inductive element is connected between an input node and first switch element. The first capacitive element, connected between the first switch element and ground, provides a first boost output voltage. The second inductive element is connected between the main switch element and first capacitive element. The second switch element is connected to a common node of the second inductive element and main switch element. The second capacitive element, connecting the second switch element to a first node, provides a second boost output voltage. The assistant switch element is connected between the first inductive element and common node of the second inductive element and main switch element.
Type:
Grant
Filed:
January 6, 2010
Date of Patent:
June 12, 2012
Assignee:
National Taiwan University of Science and Technology
Abstract: To provide a semiconductor light emitting device with a light extraction efficiency increased and a method for manufacturing the semiconductor light emitting device. A semiconductor light emitting device 1 includes a supporting substrate 2 and a semiconductor stack 6 including an MQW active layer 13 emitting light and an n-GaN layer 14 at the top. In the upper surface of the n-GaN layer 14 of the semiconductor attack 6, a plurality of conical protrusions 14a are formed. The protrusions 14a are formed so that an average WA of widths W of bottom surfaces of protrusions 14 satisfies: WA>=?/n, where ? is wavelength of light emitted from the active layer and n is a refractive index of the n-GaN layer 14.
Abstract: A method of manufacturing a semiconductor device on a semiconductor substrate, includes the steps of forming a first metal film on a front surface of the semiconductor substrate; forming a second metal film on the surface of the first metal film; activating a surface of the second metal film to provide an activated surface; and forming a plated film on the activated surface by a wet plating method in a plating bath that includes a reducing agent that is oxidized during plating and that has a rate of oxidation, wherein the second metal film is a metal film mainly composed of a first substance that enhances the rate of oxidation of the reducing agent in the plating bath. Wet plating is preferably an electroless process.
Abstract: A liquid crystal display and the driving method thereof. The LCD includes a timing controller, a plurality of driver chips and a display panel. The driver chips are cascaded together for driving the display panel to display frames. A driver chip includes a differential receiver, a single-ended receiver, a shift register, a differential transmitter, a single-ended transmitter and a pixel driver. The driver chip receives a pixel signal and drives the display panel according to the pixel signal, and outputs the pixel signal to the next driver chip.
Type:
Grant
Filed:
April 15, 2009
Date of Patent:
June 12, 2012
Assignee:
AU Optronics Corp.
Inventors:
Chih-Sung Wang, Chih-Hsiang Yang, Chao-Liang Lu