Abstract: A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is located above the substrate. A channel zone of the first conduction type is formed in the first layer. A first terminal zone of the second conduction type is configured adjacent the channel zone. A second terminal zone of the first conduction type is formed in the first layer. Compensation zones of the first conduction type are formed in the first layer. A second layer of the second conduction type is configured between the substrate and the compensation zones.

Abstract: A drive train controller of a motor vehicle has an engine controller for controlling the variables that influence the torque of the engine. The drive train controller also includes a transmission controller for controlling the gear shift operations of the automatic transmission. The transmission controller includes a detection circuit for determining the respective driving situation of the motor vehicle. The transmission controller changes the transmission ratio in a manner that is adaptively matched to the dynamics of the determined driving situation and/or the driver characteristics.

Abstract: A decoding device includes a signal-conditioning device for generating an intermediate signal from an input signal, a data register for storing a time section of the intermediate signal and a bit decoder for converting the intermediate signal into an output signal having at least one bit. The decoding device also includes a pattern recognition device. The decoding device enables even severely disturbed signals to be reliably detected and correctly decoded. Simple adaptation of the decoding device to various uses is possible. A smart card including the decoding device is also provided.

Abstract: An hydraulic damping mount has an outer sleeve, an inner sleeve for securing thereto a piston of a spring strut (activatable in at least one direction), an elastomeric body and two chambers. The two chambers are interconnected via a gap. The inner sleeve comprises a radially projecting boss separating the two chambers from each other. The connection between the two chambers is configured in accordance with the invention as a gap between the boss and the outer sleeve so that when activated, the fluid flow through the gap is in the direction opposite to the movement of the boss, resulting in a reduction in the stiffness. This simplifies assembly whilst enhancing the stiffness response of the mount. The invention relates furthermore to a mount for supporting a spring strut in making use of such a mount.

Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: A method for estimating a channel impulse response of a mobile radio channel is described. The mobile radio channel is accessed over a wide bandwidth by a code division multiplex method. A second mobile radio channel continuously transmits sequences to a multiplicity of mobile radio receivers, and the sequences are known to each of the multiplicity of mobile radio receivers. The delay parameters of the mobile radio channel are estimated using the sequences transmitted via the second mobile radio channel. The mobile radio receiver is adjusted in accordance with the delay parameters estimated and weighting factors of the mobile radio channel are determined.

Abstract: The present invention relates to a high-voltage semiconductor component having a semiconductor substrate of a first conduction type on which a semiconductor layer is provided as a drift path that takes up the reverse voltage of the semiconductor component. The semiconductor layer is either of the first conduction type or of a second conduction type that is opposite the first conduction type. The semiconductor layer is more weakly doped than the semiconductor substrate. Laterally oriented semiconductor regions of the first and second conduction types are alternately provided in the semiconductor layer. Furthermore, the present invention relates to a high-voltage semiconductor component having a MOS field-effect transistor that is formed in a semiconductor substrate and has a drift path that is connected to its drain electrode.

Abstract: In accordance with the USB specifications, an accuracy of 0.25% is required for the data transmission rate. To generate a clock signal that allows this accuracy, the invention uses a clock generator unit that does not require a crystal. The clock generator unit includes an internal clock generator, a pulse counter that is connected to the internal clock generator, a pulse number memory, and a pulse filter. The pulse counter counts the number of internally generated clock pulses between two pulses of the synchronization signal, which are transmitted in accordance with the USB specification. The difference between the ascertained pulse number and a nominal pulse number is evaluated and is used for controlling the pulse-suppressing pulse filter. This results in a stabilized clock signal.

Abstract: The circuit forms an edge-triggered D-Flip-Flop with a master/slave configuration. The master circuit has only one master switch controlled by a clock signal and followed by a first inverter. The slave circuit has a slave switch followed by a second inverter and a regenerative feedback-loop. The master and slave switches can easily be realized using n-MOS-transistors instead of transmission gates, thus achieving small chip area. The Flip-Flop can easily be amended by set and reset devices and it is suitable for mass applications such as memory and microprocessor chips.

Abstract: A rechargeable battery unit, which is intended for supplying a voltage to an electrical appliance, is charged by an external charging voltage by a charging circuit. The charging circuit is configured such that a charge regulator controls the charging process, and a monitoring unit monitors the voltage that is applied to the rechargeable battery unit and causes the charging regulator to limit the voltage that is applied to the rechargeable battery unit if any over-voltage occurs.

Abstract: A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.

Abstract: In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.

Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A semiconductor component includes a semiconductor body of a first conductivity type which accommodates a space charge region. Semiconductor regions of a second conductivity type are disposed in at least one plane extending essentially perpendicularly to a connecting line extending between two electrodes. A cell array is disposed under one of the electrodes in the semiconductor body. At least some of the semiconductor regions of the second conductivity type are connected to the cell array via filiform semiconductor zones of the second conductivity type in order to expedite switching processes. A method for fabricating such a semiconductor component is also provided.

Abstract: A device for forming an image on a printing plate includes at least one laser, and an optical system for forming an image of radiation from the laser on the printing plate, the laser radiation having ultrashort pulses with a duration of less than 1 ns; a printing unit having at least one of the imaging devices; and a printing machine with at least one of the printing units.

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract: A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, as well as a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit. In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off. A reduced current consumption can be achieved by the present invention in this way.

Abstract: A method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way. On a semiconductor structure, in depressions on the surface, in particular below the first metal structure plane, a diffusion barrier layer is deposited, preferably with the aid of plasma-enhanced vapor phase deposition, during which the ions contained in the plasma are accelerated perpendicularly to the surface, resulting in non-conformal deposition of the diffusion barrier layer.