Abstract: A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.

Abstract: A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.

Abstract: A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to the first group of transistors, and a second load coupled to the second group of transistors, and a first group of switches and a second group of switches. Each switch in the first group of switches is selectively connected to a transistor from the first group of transistors to the first current source or the second current source. Similarly, each switch in the second group of switches is selectively connected to a transistor from the second group of transistors to the first current source or the second current source, accordingly.

Abstract: A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.

Abstract: A SiGe ESD power clamp in a Darlington type configuration where the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that of the clamping device, and a frequency cutoff that is higher than that of the clamping device.

Abstract: A duty-cycle correction circuit corrects a clock with arbitrary duty-cycle to a 50% duty-cycle clock, with its original frequency. The device acts to translate a non-50% duty-cycle clock to an accurate 50% duty-cycle clock by utilizing a divide-by-2 frequency divider and a multiply-by-2 clock doubler to achieve conversion. The duty-cycle correction circuit increases the translation back to its original frequency while using an analog negative feedback to maintain an accurate 50% duty cycle.

Abstract: Disclosed is a static CMOS circuit having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit coupled to the output; and a slow CMOS circuit fabricated from thick oxide devices coupled between the input and the output.

Abstract: An active voltage divide circuit is disclosed. The voltage divider circuit includes a pair of complementary inputs separated by a common input signal node, a pair of complementary outputs, and a pair of divider circuits coupled between the pair of complementary inputs and the pair of complementary outputs. The pair of divider circuits divide input voltages at the pair of complementary inputs, and produces the divided input voltages appear at the pair of complementary outputs, respectively.

Abstract: An enhanced 2.5V LVDS driver with 1.8V technology for 1.25 GHz provides high speed performance for off chip drivers. Level shifting is accomplished in predriver circuits with buffer amplifier circuits operating at the on chip operating voltage level driving differential amplifiers operating at the higher driver circuit operating voltage level. An enhancement circuit is interposed between the level shifting circuits and the output stage, and this enhancement circuit speeds up the switching times of the signals input to the output stage. The enhancement circuit comprises first and second complementary transistors connected in cascode between the higher driver circuit operating voltage and a third transistor connected between the node of a predriver circuit and the higher supply voltage. The gate of the third transistor is connected to a common node between the first and second transistors.

Abstract: A method and structure for a body coupled driver circuit includes a pull-up stage having a first transistor and a pull-down stage having a second transistor. The first transistor and the second transistor have bodies coupled to either a reference voltage or a pad node.

Abstract: A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.

Abstract: ESD (Electrostatic Discharge) robust current mirror circuits incorporate circuitry for decoupling the gate when the chip is unpowered. Additional protection is provided by a second element which provides de-biasing to prevent Vgs from being established. A third element can be added between the gate and the ground potential on the current mirror gate node to prevent the gate of the current mirror from rising too high and allows the current to be discharged through the element instead of the current mirror.

Abstract: A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations.

Abstract: A semiconductor device which comprises an anode of a first conductivity type; a cathode of a second conductivity type; a device region separating said anode and said cathode, said device region comprises at least a gate dielectric; and an overvoltage control network coupled to the gate dielectric of said device region, wherein said overvoltage control network substantially reduces electrical overstress of said gated device.

Abstract: A latch device having a selectable feedback path includes a retaining device and system isolation device. The retaining device retains within the feedback path a logical value to be written out. The logical value is latched during an active clock signal. The system isolation device disconnects the retaining device from the feedback path during a write operation. Then, when the logical value is written out, the system isolation device reconnects the retaining device. Thus, the feedback path of the latch device may be disconnected to allow for a change in the latch state without overdriving a feedback inverter.

Abstract: The method and system of the present invention provides for a test tool consisting of a Test nano Kernel and supported test programs (exercisers) which sequentially stage validity tests for central complex electronics hardware for architecture and hardware implementation for a single processor or in a multiprocessor system. Central electronics complex hardware is a processor, memory sub-system and system bridge coupled together and may include the input/output ports. Each stage becomes increasingly complex as the hardware platform becomes more stable. The Test nano Kernel consists of approximately 500 K of software code, provides multiprocessor support and implements context and 64-bit execution, effective equal to real and shared memory service, segment register attachment, gang scheduling and CPU affinity services. The Test nano Kernel provides for a smooth transition from simulation due to its capabilities to run simulation test cases on real hardware.

Abstract: A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

Abstract: A method and apparatus for enhancing reliability of a high voltage input/output (I/O) driver/receiver reduces voltage stress on transistors forming part of a logic I/O driver/receiver. The driver/receiver is designed to handle voltages greater than the power supply rails and a bias circuit reduces the voltage stress present on the output stage when a power supply voltage is removed from the circuit. The bias circuit is driven by I/O pin voltage to control a transistor within the I/O logic ladder.

Abstract: A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations.

Abstract: An automated software test is provided which includes a functional model of a system to be tested. The automated software test is utilized to operate a system under test in accordance with specified facts, goals and rules. Quasi-random actions are taken within the system in accordance with specified rules and facts until a defined goal has been accomplished. Training the automated software test is accomplished by specifying a particular goal, i.e. identifying a particularly known defect, and thereafter running the test in a quasi-random fashion until the particular goal has been achieved. The number and nature of actions required to achieve that goal are logged and the process is then repeated until the shortest path required to achieve that goal has been determined. The log of actions which eventually reach a particularly defect may also be utilized a probable cause tree structure for future analysis.