Abstract: Cache and architectural functions within a cache controller are layered so that architectural operations may be symmetrically treated regardless of whether initiated by a local processor or by a horizontal processor. The same cache controller logic which handles architectural operations initiated by a horizontal device also handles architectural operations initiated by a local processor. Architectural operations initiated by a local processor are passed to the system bus and self-snooped by the controller. If necessary, the architectural controller changes the operation protocol to conform to the system bus architecture.

Abstract: A method of allocating a cache used by a processor of a computer system between instructions and data is disclosed. Program instructions are loaded in the processor for monitoring relative usage of the cache by each value class and selecting a desired ratio of cache usage by the classes from among a plurality of available ratios, and cache blocks within the cache are evicted using a cache-replacement mechanism which restricts replacement of an evicted cache to a particular one of the classes of values (instruction or data) based on the desired ratio of cache usage. A multi-bit facility may be provided to indicate how to confine a selected victim to certain cache blocks, and the program instructions select the desired ratio of cache usage by setting the multi-bit facility. The cache-replacement mechanism can be a modified least recently used replacement mechanism. Different instruction/data ratios thereby may be provided, such as 1:1, 1:2, and 2:1.

Abstract: A method and system for speculatively sourcing data from a cache memory within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then sourced from a cache memory within the second processing unit by driving the requested data onto a system data bus before a combined response from all the processing units returns to the second processing unit.

Abstract: There is provided a prerecorded stored data file of a sequence of keystrokes and interactive display cursor selections for controlling the subsequent configuration of a network comprising a plurality of server computers and a plurality of client computers. This data file is created by predetermining the components and the programs to be supported by each of said server and client computers in said network and the configuration of said network, making the interactive keystroke and cursor entries required to install said predetermined components and programs on said server and client computers through the display interface of a primary one of said server computers and making the interactive keystroke and cursor entries required for further configuration of said network through said display interface. This sequence of said entries in a recorded data file in said primary server computer.

Abstract: In multi-processor systems which have separated the system bus from the I/O bus, a Shadow Directory is introduced into the memory controller for reducing bottlenecks that occur from the processors snooping data cache in the I/O devices residing on the I/O bus. This Shadow Directory is advantageously employed in a system, such as the PowerPc architecture which distinguishes between the types of data that can be cached in I/O devices. The Shadow Directory uses two First In First Out (FIFO) stacks for two different types of data. These FIFO stacks are then used for addresses placed on the system bus and I/O bus in order to reduce snoop latency times.

Abstract: A method and system in a remote computer network for allowing users to customize on-line search engines for on-line data searches. An on-line search engine is provided at a remote network site, such that the on-line search engine may be displayed at local network sites linked to the computer network. An independent user-defined search plug-in program is then designated for limiting the scope of online data searches to particular data subjects, such that the user-defined search plug-in program is called for processing by the on-line search engine during on-line data searches by the on-line search engine at a local network site utilizing search terms. The independent user-defined search plug-in program is subsequently stored at the local network site.

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. Program instructions in the processor select a second associativity level of a known appropriate level, and implement the second associativity level in the cache using a second mapping function. Application software may provide the program instructions, wherein the application software has procedures that may result in cache "strides" at particular associativity levels, and the known appropriate level is chosen to lessen memory latencies due to strides. Alternatively, the program instructions may be part of an operating system which monitors memory address requests, determines how efficient a procedure will operate at different associativity levels, and selects a most efficient level for the known appropriate level.

Abstract: The present invention defines a means for establishing a secure connection between a Java Applet and a secure web server for protocols other than Https via the use of a Java Security Service. More specifically, the present invention uses the web browser's installed certificates to setup and establish an encrypted session between the Java Applet and the secure web server. The secure connection is then used to retrieve the certificates required by the Java security service.

Abstract: A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.

Abstract: A multiprocessor data processing system includes a shared main memory and a plurality of processors connected to the memory utilizing a system bus. Data is transferred utilizing the system bus. The plurality of processors include a first processor and a second processor. The first processor includes a first cache, and the second processor includes a second cache. The multiprocessor data processing system executes a test program. During execution of the test program, a first and a second trace are generated. The first trace is generated by monitoring all events occurring at a first location within the system. The second trace is generated by monitoring all events occurring at a second location within the system. Each event is associated with a time of occurrence of that event. The first trace includes each event which was monitored at the first location and the time associated with each event.

Abstract: A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data to the second bus having the second ordering policy. The apparatus includes at least one first unit for a first class of operations, each first unit being assigned to a single first class operations at a time. The apparatus also includes at least one second unit for a second class of operations, each second unit being assigned to a single second class operation at time. The apparatus also includes intra prioritizing circuitry, for each class of operations, for prioritizing the assigned operations according to the second ordering policy exclusive of the operations stored in the other classes.

Abstract: A method of accessing electronic information, by loading an original document onto a data processing system, selecting a link embedded in the original document (wherein the link is associated with a linked document), and creating a new document by merging the linked document with the original document. Other new documents can similarly be created by merging additional linked documents with the earlier new documents in response to the further selection of other links embedded in the new documents. The original document and one or more linked documents can thus be displayed as a single, unitary file, as well as being printed as a single document. The linked document can be merged with the original document in a variety of manners. The invention is particularly useful in accessing hypertext pages on the World Wide Web of the Internet.

Abstract: A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses. Each one of the execution units are assigned to a group which represent a class of operations. The apparatus further includes intra prioritizing means, for each group, for prioritizing the stored operations according to the second ordering policy exclusive of the operation stored in the other group. The system also includes inter prioritizing means for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.

Abstract: A method, apparatus, and article of manufacture for directing a computer system, having at least a processor, user controls, and computer display, to automatically resize a window displayed on the computer display. The method includes the first step of in response to a command from user controls over a first portion of the window, determining whether the window is zoomed out. The second step includes if the window is not zoomed out, automatically resizing the window to a smaller size while continuing to display the contents of the window. The third step includes re-displaying on the computer display the window using the smaller size.

Abstract: A method and implementing system 101, are provided in which a computer system is arranged for connection 210 to a network system such as the Internet. A user of the computer system may selectively display 401 a listing of network data path and site history files from previous network sessions, and select one or more items from the list for modification 407, 409, 411. The user may then modify the current history file by creating 411, 701 a new current history file. A new current history file may also be modified by exchanging 407, 501 or appending 409, 601 the selected and modified selected items with the current history file to create a new current history file. The newly created history file then includes data paths and/or portions thereof, which were successfully used in previous network sessions.

Abstract: A method of dynamically avoiding defective cache lines in a cache used by a processor of a computer system is disclosed. A repair mask is used, having an array of bit fields each corresponding to a cache lines in the cache, and certain bit fields in the repair mask array are initially set to indicate that a group of corresponding cache lines are defective. Thereafter the repair mask is updated by setting additional bit fields in the repair mask array to indicate that an additional group of corresponding cache lines are defective. Access to all defective cache lines is prevented based on the corresponding bit fields in the repair mask array. The initial setting of certain bit fields can take place at fabrication of the cache chip in response to testing of the cache lines. Additionally, the repair mask may be updated each time the computer system is booted in response to testing by the boot procedure.

Abstract: A system and method are provided that allows the results of an instruction trace mechanism to globally restructure the instructions. The process reorders the instructions in an executable program, using an actual execution profile (or instruction address trace) for a selected workload, to improve utilization of the existing hardware architecture. The reordering of instructions is implemented at a global level (i.e., independent of procedure or other structural boundaries which maximizes speedup) running on various hardware platforms and adds the ability to preserve correctness and debuggability for reordered executables. An unconditional branch instruction is added at the memory locations where reordered instructions previously were stored. When a dynamic branch occurs, the program will attempt to access the instruction at the original address and the unconditional branch directs the program to the reordered location of the instruction and program integrity is maintained.

Abstract: A method and apparatus is provided in which a data file acquisition program is operable to determine the data transfer speed of a plurality of devices containing a predetermined data file. The methodology calculates a priority ordering of the devices based upon the data transfer speed, and divides the data file request into portions for parallel access and delivery of the requested data file such that all of the portions are delivered to the user at approximately the same time whereby faster devices will be requested to access and deliver larger file portions and relatively slower devices will be assigned to access and deliver relatively smaller portions of the requested data file. Upon receipt of the portions, the requested data file is assembled for further processing by the user.

Abstract: A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. Program instructions are loaded in the processor for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes is then defined using a mapping function which operates on the encoded addresses, such that the program instructions may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The program instructions can modify the original addresses by setting a plurality of programmable fields. Application software may provide the program instructions, wherein congruence classes are programmed based on a particular procedure of the application software which is running on the processor, that might otherwise run with excessive "striding" of the cache.

Abstract: A method and implementing computer system is provided including a multimedia server connected in a network configuration with client computer systems. The multimedia server includes various functional units which are selectively operable for delivering and effecting the presentation of multimedia files to the client such that a plurality of multimedia files are seamlessly concatenated on the fly to enable a continuous and uninterrupted presentation to the client. In one example, client selected video files are seamlessly joined together at the server just prior to file delivery from the server. The methodology includes the analog to digital encoding of multimedia segments followed by a commonization processing to ensure that all of the multimedia segments have common operating characteristics.