Abstract: A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request.

Abstract: A method of accessing files located in a computer system, by selecting a plurality of embedded links (such as hypertext links) from one or more pages displayed in a browser window, and processing the plurality of embedded links concurrently. The embedded links may include at least two embedded links from a single page displayed in the browser window, or may include at least one embedded link from a first page and at least one other embedded link from a second page. In one implementation, a pop-up menu is displayed once the links have all been selected, wherein the pop-up menu has a plurality of menu items associated with different types of link processing.

Abstract: A method of controlling eviction of cache blocks to override eviction of a value which is reserved for a later operation. When a value is loaded into a cache of the processor and is reserved using a lwarx instruction, it sometimes is evicted from the cache due to the need to store other values in the cache set that the value is mapped to. The present invention provides a method of overriding eviction of reserved values by evicting a selected block of the cache which is a block other than the block containing the reserved value. The reserved value is indicated as being reserved by loading a memory address associated with the value into a reservation unit of the cache, and making a reservation flag in the reservation unit active.

Abstract: A network of a server and a plurality of client computers for small businesses which is easy to install, configure and operate and still provides all of the users in the business with the same transparent access to all of their allocated software resources through a same graphical user interface irrespective of which one of the client computers in the network they may sign onto. The operating systems and the application programs to be used on the client computers are loaded on the server. The users have been prompted for the one time input of data required by the server computer to allocate an operating system and application programs for use by each of a plurality of users on each of the plurality of client computers.

Abstract: A method and apparatus for preventing the occurrence of deadlocks from the execution of variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. Execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others. The snoopers initiate operations at the same time based upon a common predefined event and ensure the operations end are finished concurrently when no outstanding retry operations are detected.

Abstract: A system is provided for setting up what is in effect a “plug and play” local area network for small businesses comprising a server computer and a plurality of client computers. The server computer is preloaded with a network operating system, an operating system for each of the client computers and substantially all application programs to be used by the client computers. There is a programmed interactive display interface in the server computer for interactively prompting a user to make a sequence of data entries relative to the computing needs of the client computers and the users of the client computers. The server computer is then physically interconnected with the client computers. Then means in the server computer allocate the client operating systems and the application programs as needed by the user of the client computers based upon the set up resulting from the prompted data entries.

Abstract: A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock.

Abstract: A method and apparatus for detecting whether dynamic logic circuits are precharging properly. The method and apparatus uses a narrowed reset pulse to verify precharging is occurring as designed.

Abstract: A method and apparatus of a computer based security system to prevent unauthorized access to computer-stored information comprising several components. These comprise of an intrusion detection mechanism, a ROM-based firmware program, an internal battery sized to provide several minutes of operation of the computer system and all its internal devices, and a mechanism to reset the central processing unit of the computer and switch to battery power responsive to the intrusion detection mechanism.

Abstract: A data processing system has a reader device adapted to read information residing on a first type of storage article (such as a floppy diskette), and a holder is provided which is substantially identical in size and shape to the first type of storage article, but allows the reader device to read a card which bears machine-readable information, such as a credit card. The holder can have a slot therein for receiving the card, which is aligned within the holder to position a portion of the information medium at an access area of the holder. The machine-readable information can be, for example, encoded on a magnetic strip on the card. The system allows network-based transactions which read from the card as well as write to it.

Abstract: The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of singly-initiated singly-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

Abstract: A method for providing voice dynamics of human utterances converted to and represented by text within a data processing system. A plurality of predetermined parameters for recognition and representation of dynamics in human utterances are selected. An enhanced human speech recognition software program is created implementing the predetermined parameters on a data processing system. The enhanced software program includes an ability to monitor and record human voice dynamics and provide speech-to-text recognition. The dynamics in a human utterance is captured utilizing the enhanced human speech recognition software. The human utterance is converted into a textual representation utilizing the speech-to-text ability of the software. Finally, the dynamics are merged along with the textual representation of the human utterance to produce a marked-up text document on the data processing system.

Abstract: A method of managing and speculatively issuing architectural operations in a computer system. A first architectural operation is snooped and translated into a plurality of granular architectural operations to effect a large-scale architectural operation. The first architectural operation can be a first cache instruction directed to a memory block, and a plurality of cache instructions are issued which are directed to memory blocks contained in a page associated with the memory block. The granular architectural operations are transmitted to a processor bus of the computer system. A processor bus history table may be used to store a record of the large-scale architectural operation. The history table then can filter out any later architectural operation that is subsumed by the large-scale architectural operation. The history table monitors the processor bus to ensure that the large-scale architectural operations recorded in the table are still valid.

Abstract: A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock.

Abstract: A method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

Abstract: A method and system of providing a pseudo-precise inclusivity scheme in a sectored cache memory for maintaining cache coherency within a data-processing system is disclosed. In accordance with the method and system of the present invention, a cache memory includes a multiple of cache lines. The data field of the cache lines is divided into multiple sectors. A state-bit field is associated with each of the cache lines, and the state-bit field is utilized to identify at least four different states of the corresponding cache line. An inclusive-bit field is associated with each of the sectors within each cache lines, and the inclusive-bit field is utilized to identify an inclusivity state of an associated sector. A first of the four states is assigned to provide precise inclusivity states of an associated cache line. A second and a third of the four states is assigned to provide an imprecise inclusivity state of an associated cache line for improving cache line state decoding efficiency.

Abstract: A method and apparatus for Chemical-Mechanical Polishing of semiconductor wafers using various formulations of high viscosity slurry.

Abstract: A method is disclosed of managing architectural operations in a computer system whose architecture includes components having varying coherency granule sizes. A queue is provided for receiving as entries a plurality of the architectural operations, the entries of the queue are compared with a new architectural operation to determine if the new architectural operation is redundant with any of the entries. If the new architectural operation is not redundant with any of the entries, it is loaded in the queue. The computer system may include a cache having a processor granularity size and a system bus granularity size which is larger than the processor granularity size, and the architectural operations are cache instructions. The comparison may be performed in an associative manner based on the varying coherency granule sizes.

Abstract: A method and apparatus for detecting and initializing the addition of a new client machine to a network while requiring only minimal intervention by an individual. The above is accomplished by using the unique network adapter addresses, for each client of the network, to determine whether or not existing client machines are operative, as well as the addition of a new client machine to the network. Upon the detection of the addition of a new client machine, the new client machine is initialized using profiles and templates to default parameters, and is fully operative with minimal interaction by an individual.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.