Abstract: A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache.

Abstract: A method for checking security of data received by a computer system within a network environment is disclosed. In accordance with a preferred embodiment of the present invention, an incoming packet from a client is first decrypted within a receiving communications adapter by utilizing a master decryption key. The decrypted incoming packet is then encrypted by utilizing an encryption key identical to an encryption key employed by the client. A determination is made as to whether or not a packet produced from the encryption is identical to the incoming packet. In response to a determination that a packet produced from the encryption is identical to the incoming packet, the decrypted incoming packet is forwarded to a system memory of the computer system. As such, any incoming packet that does not meet this criterion will be rejected as a security threat.

Abstract: A method of changing the functionality of a statically bound device driver, by dynamically extending the static device driver using a registered driver extension. The static device driver has a plurality of handlers or functions (such as input/output functions) used to control a device that is connected to or part of the computer system, and the driver extension modifies at least one of these functions, although it can be used to change several, or even all, of the functions. In the embodiment wherein the computer system is a UNIX-type workstation having a kernel residing in the memory, the static device driver is loaded in the kernel and is dynamically extended by providing at least one entry point for the driver extension.

Abstract: A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information.

Abstract: In a data processing system including a bus connected to a plurality of devices capable of driving said bus, error reporting and isolation is achieved by signaling a self-check to each device connected to the bus to determine if it was driving the bus at the time an error occurred. The bus check request is generated by one of the devices connected to the bus in response to detecting either a parity error or an internal error. If a parity error is detected, a bus check request is signaled to a combining unit connected to the bus. The combining unit signals the self-check to each of the devices attached to the bus in response to receiving the bus check request. Each device determines whether it was driving the bus at the time the error occurred and, if so, sets a source of error indicator on the device. Similarly, if an internal error is detected, the detecting device sets source of error and internal error indicators on the detecting device and signals a bus check request to the combining unit.

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.

Abstract: A method and apparatus for providing the user of a computing device displaying information to control the navigational aspects of the displaying while retaining ease of use and other desireable characteristics. Specifically, the user is provided with an opaque box having a dot located in the center which can be dragged and dropped. The dragging and dropping of the dot controlling the distance and direction with which the information is moved.

Abstract: Cache and architectural specific functions within a cache controller are layered to permit complex operations to be split into equivalent simple operations. Architectural variants of basic operations may thus be devolved into distinct cache and architectural operations and handled separately. The logic supporting the complex operations may thus be simplified and run faster.

Abstract: A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.

Abstract: A method and apparatus for maintaining a list for threads which are awaiting their occurrence of event. First a thread is detected that desires to perform some type of action based upon the occurrence of an event. Thereafter, the value of an event list anchor is set to indicate that it is currently unavailable. Thereafter, the value of the event list anchor set equal to the identification of the second thread.

Abstract: A high-level (L2) cache and a efficient method for writing directory entries into an array of directory entries are disclosed. The high-level (L2) cache operates differently depending upon whether a MESI (Modified, Exclusive, Shared, Invalid) state of a cache line in Invalid or Modified when the cache line's low-level (L1) Inclusive bit is set. Initially, the high-level (L2) cache retrieves a directory entry from the array of directory entries. This directory entry is placed into an n-position priority queue. Associated with the n-position priority queue is a set of priority indicators. These priority indicators are updated when a directory entry is placed into the n-position priority queue to indicate which order the various directory entries were placed into the n-position priority queue. If the directory entry is waiting for results to be received from the system bus, the directory entry will remain in the queue until such results are received.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, and the cache transmits a response indicating that the cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead.

Abstract: An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler.

Abstract: A data processing system and method of communicating data in a data processing system are described. The data processing system includes a communication network to which a plurality of devices are coupled. At least one device among the plurality of devices coupled to the communication network includes mastering circuitry and snooping circuitry. According to the method, a first timing signal having a first frequency and a second timing signal having a second frequency different from the first frequency are generated. Communication transactions on the communication network are initiated utilizing the mastering circuitry, which operates in response to the first timing signal, and are monitored utilizing the snooping circuitry, which operates in response to the second timing signal.

Abstract: A method of using a debugger for a computer operating system by providing a statically bound debugger driver which can be used early in the boot process, and further providing one or more dynamic debugger drivers which can be loaded after system initialization. The core portion of the operating system, such as the kernel for a UNIX-type workstation, makes a determination of whether any hardware device is connected to the computer that is of the type of debugger devices supported by the statically bound driver; if so, then the debugger can be used early in the boot process, but if not, provision is made for calling the dynamic debugger driver from some other portion of the operating system software, such as from the boot filesystem or PAL. The dynamic debugger driver may be selected from a plurality of dynamic debugger drivers, the particular selected dynamic debugger driver being associated with the particular hardware device that is actually connected to the computer.

Abstract: A method of bypassing defects in a cache used by a processor of a computer system. A repair mask has an array of bit fields corresponding to cache lines in the cache, and when a particular cache line in the cache is identified as being defective, a corresponding bit field in the repair mask array is set to indicate that the particular cache line is defective, and further access to the defective cache line is prevented, based on the corresponding bit field in the repair mask array. The repair mask can be used to prevent the defective cache line from ever resulting in a cache hit, and to prevent the defective cache line from ever being chosen as a victim for cache replacement. Using a set associative cache, the defective cache line is thereby effectively removed from its respective congruence class. This approach allows the cache to use all non-defective cache lines without any cache lines being reserved for redundancy.

Abstract: A method and system for front-end and back-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, the store queue includes a front-end queue and a back-end queue. In response to a determination that the data field of the first entry of the front-end queue is not filled completely, another determination is made as to whether or not an address for a store instruction in a subsequent second entry is equal to an address for the store instruction in the first entry plus a byte count in the first entry. If so, the store instruction in the subsequent second entry is collapsed into the store instruction in the first entry.

Abstract: A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses. Each one of the execution units are assigned to a group which represent a class of operations. The apparatus further includes intra prioritizing means, for each group, for prioritizing the stored operations according to the second ordering policy exclusive of the operation stored in the other group. The system also includes inter prioritizing means for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.

Abstract: A method and system for marking and subsequently retrieving a collection of objects contained within a compound document. The compound document is displayed within a graphical user interface within a data processing system. The graphical user interface includes a scroll bar. A collection of objects within a portion of the compound document may be selected by a user. Thereafter, a horizontal line is displayed within the scroll bar which corresponds to the relative location of the collection of objects within the compound document. Next, in response to a user input, a dialog box is displayed at a location adjacent the horizontal line. The graphical user interface next prompts a user to enter within the dialog box a label and attributes of the collection of objects.