Abstract: A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth clock waveform ranging in phase from zero (0) to 32&pgr; radians. An interpolator detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length, and a phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2&pgr; radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length, and the phase detector measures a second phase increment when the second zero-crossing transition is detected.

Abstract: An electronic device is described, for a timepiece of electronic or electromechanical type, comprising a source of electrical power (4), such as a battery, an electronic circuit (3) and an electrical connector tongue (5) effecting an electrical connection between the source of electrical power and the electronic circuit. The electrical connector tongue (5) has first and second openings (55, 56) cooperating with a pair of fixing pins (25, 26) fixed to a support (2) of the said device, and further comprises a section (57) formed between the said openings (55, 56) and adapted to deform in an elastic manner so as to alter the spacing between the openings (55, 56) and allow engagement and retention of the electrical connector tongue (5) on the fixing pins (25, 26).

Abstract: An adder circuit uses a summing circuit to provide a summed sliced bit number from a first sliced bit number and a second sliced bit number. A boundary circuit is operably connected to the summing circuit to form a rounding boundary between selected groups of the summed sliced bit number. A rounding circuit is operably connected to the boundary circuit to detect a zero in each slice of the summed sliced bit number while the first and second sliced bit numbers are being added to one another. The rounding circuit includes a logic circuit to detect the zero and provide a zero detect output and a control circuit to selectively round the summed sliced bit number up and down in response to the zero detect output.

Abstract: A technique for supplying drive voltage to the gate of a high-side depletion-mode N-channel MOS-device for phase-leg circuits, H-bridges, or any circuit with a depletion-mode N-channel MOS-device with its source at a voltage above local ground.

Abstract: A buried layer of dopant is formed in a semiconductor by etching a series of trenches, then depositing dopant at the bottom of the trenches and diffusing until the dopant from different trenches meet to form a continuous layer. Depending on the material used to fill the trenches, the buried layer can be contacted or isolated. With this method, it becomes unnecessary to grow expensive epitaxial layers.

Abstract: An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to the data memory and the program decoder and includes two Arithmetic Logic Units that are used to generate the X and Y operands. Each alu a has a triplet of registers associated there with and include a linear path of a first DBLC adder. The first DBLC adder has an A input, a B input, a carry input connected to receive a first control signal, and a summation output. The linear path further includes a by pass connection for by passing the first DBLC adder. A multiplexer selects either the summation output or the by pass as a linear output. Each alu also includes a modulo path that is in parallel with the linear stage. The modulo path has a series connection of a Carry Sum Adder (csa) and a second DBLC adder with a modulo output. A second multiplexer selects either the linear output or the modulo output as a result.

Abstract: A computer, such as a PC includes a memory having an imaging program stored in it and a display unit, such as a restor scan CRT are all operatively connected together so that the computing unit can generate a signal that will result in an image being displayed on the display unit. The image includes a moveable figure that moves in response to inputs being provided via an input terminal, towards a set of targets. In response to the inputs from the input terminal, the computer initiates a set of actuators to move the figure wherein each actuator defines the movement in a given plane.

Abstract: Proprietary information such as programs and/or data are protected using a secure processing system that includes a memory such as an EPROM in which the proprietary information is stored in a first portion of the memory. The stored information is encrypted by an encryption algorithm unique to the proprietor of the information. The stored information is assigned an unique key that will enable the information to be decrypted if the unique algorithm is known. A second portion of the memory has the unique key stored therein, the unique key is encrypted with a master encryption algorithm and can only be obtained by using a master key with the master algorithm. A processing unit such as a Digital Signal Processor (DSP) has both the proprietor's unique algorithm, master algorithm and master key available to it.

Abstract: A control system for a bidirectional switch (20) is described, formed of a pair of MOFSET power transistors (210, 220) connected in anti-series, i.e. source to source or drain to drain. This control system includes means (50) allowing the state of conduction of the power transistors to be controlled, one or the other of these transistors being able to be set to the “OFF” state in order to assure the interruption of a current through the bidirectional switch (20). This control system includes coupling means (SWCPL, 510) enabling the gate of the power transistor at the “ON” state to be coupled at least temporarily with the gate of the power transistor at the “OFF” state when the bidirectional switch is switched on. This has the advantage of allowing, on the one hand, the use of high control voltages assuring a reduction in the series resistance of the power transistors, and, on the other hand, the bidirectional switch to be quickly switched on.

Abstract: A DC coupled serial data stream receiver system utilizing a switched capacitor based differencing front end which compares the instantaneous value of an analog voltage with respect to its long term minimum value to a series of reference voltages V1 to Vn in a flash analog to digital converter style front end. The circuit is designed to interface directly to a discrete fiberoptic preamplifier. The receiver can handle multiple amplitude serial data as produced by multiple fiberoptic transmitters on the same fiber without any data loss and without any interruption in data transfer being necessary as one transmitter halts and a second one starts transmission.

Abstract: A computer, such as a PC, includes a memory having an imaging program stored in it and a display unit, such as a raster scan CRT are all operatively connected together so that the computing unit can generate a signal that will result in an image being displayed on the display unit. The image includes a moveable figure that moves in response to inputs being provided via an input terminal, towards a set of targets. In response to the inputs from the input terminal, the computer initiates a set of actuators to move the figure wherein each actuator defines the movement in a given plane.

Abstract: A phase lock loop circuit for a digital radio generates the sampling frequency for sampling an incoming signal by storing the samples of the incoming signal in an accumulator at a first frequency. The accumulator is unloaded at the sampling frequency. A microprocessor monitors the rate in which the samples are stored in the accumulator and provides a switching signal to vary the sampling frequency in small increments to prevent the accumulator from overflowing or underflowing.

Abstract: Photosensor comprising a network (R) of cells ( . . . , Cn-1, Cn, Cn+1, Cn+2, . . . ) each comprising a photosensitive component (PH) and an exploitation circuit (CE) for allowing the transfer of a measurement signal coming from the cell ( . . . , Cn-1, Cn, Cn+1, Cn+2, . . . ) and due to the illumination of this cell, to a common output (SC) of the photosensor. An addressing signal allows to sequentially connect all the cells to said common output. According to the invention, each cell also comprises an integrated conductive region (RC) forming together with said photosensitive component (PH) a test capacitor (CPT) which is coupled to the parasite capacitor (CP).

Abstract: Proprietary information such as programs and/or data are protected using a secure processing system that includes a memory such as an EPROM in which the proprietary information is stored in a first portion of the memory. The stored information is encrypted by an encryption algorithm unique to the proprietor of the information. The stored information is assigned an unique key that will enable the information to be decrypted if the unique algorithm is known. A second portion of the memory has the unique key stored therein, the unique key is encrypted with a master encryption algorithm and can only be obtained by using a master key with the master algorithm. A processing unit such as a Digital Signal Processor (DSP) has both the proprietor's unique algorithm, master algorithm and master key available to it.

Abstract: A wafer (10) is described comprising several integrated optoelectronic circuits of a first type (11), such circuits of the first type each comprising electronic modules (13) and at least a first photodiode (14).Said wafer (10) is characterised in that it further comprises at least one integrated optoelectronic circuit of a second type (21) comprising electronic modules (23), at least one second photodiode (24) and at least one bonding pad (25) intended to be connected to an external measuring apparatus, said at least one bonding pad (25) being superposed onto said at least one second photodiode (24) so that said at least one circuit (21) of the second type may be used as a circuit for verifying the manufacturing of said wafer.

Abstract: A data receiving channel has a signal converter that converts a received signal into a digital signal. The digital signal is then applied to a Viterbi detector that will provide, as an output, a stream of digital signals that have a maximum likelihood of being accurate. Error correction is performed at the bit level through calculation of the error between the received signal and the maximum likelihood estimate signal produced by the Viterbi detector.

Abstract: A detection device has a transducer (10) for emitting and receiving series of ultrasonic pulses. An integrator (23) integrates echo signals resulting from ultrasonic pulses within a time window so as to produce an integral value. A time-delay circuit (28) is used to control the instant of opening T1 of a time window and a control circuit (25) determines an average value of a number of n integral values and for loading the values of the opening a instant T1 into the time-delay circuit (28) so as to maintain the average value at a steady value. The control circuit (25) determines the average value by loading a first value of T1 in the time-delay circuit before the integration of the first x echo signal and a second value of T1 in the time-delay circuit before the integration of the second n-x echo signals.

Abstract: An instrument heater for heating a surgical instrument. The instrument heater includes a sheath having an inner and outer wall. The inner wall forms a bore through which the optical scope is inserted. A chemical solution fills the space between the inner and outer wall of the sheath. At one end of the sheath is an activator disk having a chemical substance attached to its surface. When the activator disk is flexed, it ejects the chemical substance and interacts with the chemical solution to initiate an exothermic reaction. The exothermic reaction results in the generation of heat within the sheath, which is transmitted to the surgical instrument. Once the surgical instrument is sufficiently heated to a temperature close to the temperature of a body, the optical scope is inserted into the body. A natural tendency for the instrument to fog up is prevented by the equalizing the temperature of the instrument with the body.

Abstract: The compact disk comprise a data storage medium (2) for optical reading situated in an annular region (4), which defines a central region (6) wherein is arranged an electronic module, formed of an electronic unit (12), in particular an integrated circuit, and an antenna formed by a winding (14), made of an electrically conductive material. The electronic module allows contactless electromagnetic coupling with an electromagnetic wave transmitter-receiver able to communicate with said electronic unit. In particular, this electronic unit comprises an identification code and/or a decoding key for the data contained in said storage medium.

Abstract: An electronic device (1) has a substrate (2) of monocrystalline silicon on which is an integrated circuit (3). The integrated circuit is an oscillator containing a resonator, a maintenance circuit to cause the vibration of the resonator, and a frequency division chain. The maintenance circuit as well as the division chain are manufactured as CMOS circuits. The resonator is an integrated resonator (4) formed of a body cut out in a delimited surface part of reduced thickness (14) of the substrate (2), of a thin layer of piezoelectric material (10) deposited on at least a part (6) of the body, and of a thin metallic layer (11) deposited on the piezoelectric layer (10) so as to form an electrode.