Abstract: An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.

Abstract: A device for improving the quality of audio and/or video signals comprises a main electrical circuit comprising an integrated circuit arranged for producing an output pulse signal having a predetermined frequency, and a toroidal inductor having a magnetic core which has a central opening and which is surrounded by a conducting wire, said toroidal inductor being arranged to be powered by said output signal.The device is arranged between a power supply unit and a signal processing unit which is connected by at least a phase- and a neutral conductor to said power supply unit such that said conductors pass through said central opening of said magnetic core, said toroidal inductor creating an alternating magnetic field within its core when it is powered by said output signal, so that said magnetic field induces an electric field which acts on said conductors.

Abstract: An integrated circuit has an on-chip voltage regulator circuit. The voltage regulator circuit includes a control circuit, a pass element and a control connection and also provided is a connection for connecting an external pass element to the voltage regulator. There is a switch circuit that when an external pass element is connected to the voltage regulator, the switch circuit will turn off the internal pass element.

Abstract: The device comprises a keyboard wherein each key is associated with an underlying sensor sensitive pad which controls the input of data associated with said key in response to an application of a finger on such key, such sensitive pads being closely set together within a closed contour (V.sub.1, V.sub.2 ; V'.sub.1, V'.sub.2) having, for a user, an upper part (V.sub.1) and a lower part (V.sub.2) respectively adjacent to first and second series of pads, such device being characterized in that the areas of the pads (10, 11, 12, 13; 7, 8, 9, .div.) of the first series are on the whole greater than the areas of the pads (3 to 9; 0, ., =, +) of the second series.

Abstract: Switching apparatus for selection of pickup coils of an electric guitar having dual coil bridge humbucker pickups, dual coil fingerboard humbucker pickups and a single coil intermediate pickup. The apparatus comprises a four-gang three-way switch and a two-gang five-way switch interconnected so that the guitarist may control which combinations of pickups operate at any one time thereby providing the tonal characteristics of a STRATOCASTER, a LES PAUL or a "coil tapped" LES PAUL guitar optional "out of phase" tonalities.

Abstract: A clothes drying apparatus has the general shape of a drying sleeve with sufficient length and width to hold an article of clothing for drying. The article of clothing is placed in the drying sleeve and synch lines on each end of the drying sleeve are closed thereby retaining the article of clothing inside of the drying sleeve. The drying sleeve can then be hung out to dry.

Abstract: This application discloses circuit and method for reducing the turn-off time of a power transistor driving an inductive load. The circuit clamps the gate to source of a power transistor by using two field effect transistors as the current path across the gate and source of the power transistor. A zener diode connected from the source to gate of the two field effect transistors is used to provide high voltage protection.

Abstract: A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect.

Abstract: The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and non-redundant elements may be stress tested concurrently. Enabling capabilities contained within the redundant element circuitry selectively enables the redundant elements when a stress test signal is equal to a predetermined value, indicative of a stress test mode.

Abstract: A memory system includes two memory arrays coupled to a global data bus via respective address decode circuits. Address control circuitry defaults to the weaker memory array upon receiving a new address such that the stronger memory array will not produce false values on the bus prior to stabilization of the address and proper decode. Consequently, the weaker memory array is not faced with a situation where it must overcome the previous false signal prior to developing the proper output values on the bus.

Abstract: Fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulates fuse blowing. An integrated circuit has a plurality of addressable elements and a plurality of redundant elements, which may be used to replace defective addressable elements. Each redundant element has a non-destructive fuse circuit associated with it which may be used to enable and/or test the redundant element prior to laser repair by emulating the blowing of a fuse contained in the non-destructive fuse circuit. The non-destructive fuse circuit is comprised of a fuse connected to a control logic element, such as an inverter, wherein the control logic element is in turn controlled by a test signal. Emulation of blowing the fuse or not blowing the fuse is accomplished by the logic level of the test signal.

Abstract: Circuitry for selectably connecting the body node of drive transistors of a motor control circuit. In particular, those transistors that are turned off when operating the motor in a unipolar mode have their body nodes switched so as to be connected to a reference voltage, such as ground, during unipolar mode, and to be connected to the transistor source during bipolar mode (i.e., when the transistors are active). The circuitry also is operable to briefly connect the body nodes of the transistors to their source when the opposing drive transistor is commutated, in the unipolar mode. In this way, forward biasing of inherent diodes in the drive transistor is avoided in unipolar mode, except when useful to clamp the inductive kick of the motor coils.

Abstract: A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

Abstract: The mechanism for performing writes to the data cache memory in a cache subsystem is modified to reduce the occurrence of microprocessor wait states. Concurrently, with operation of the tag RAM, the write signal from the microprocessor propagates through the data cache up to a point in the internal circuitry of the data cache which is as close as reasonably possible to the memory cell being written. At this point in the circuitry, the write signal is gated by the Match signal from the tag RAM. Address decoding is completed prior to receiving the Match signal, such that when the tag RAM generates a "hit" Match output signal, the write signal is allowed to finish propagating through data cache internal circuitry without additional address set-up time. This allows the memory cell to be written to quickly and reduces the probability of microprocessor wait states.

Abstract: A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening.

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

Abstract: A method is provided for forming an improved poly-buffered LOCOS process by forming a pad oxide layer over a substrate. A first nitride layer is formed over the pad oxide layer and a polysilicon layer is formed over the first nitride layer. A second nitride layer is formed over the polysilicon layer. An opening is etched through the second nitride layer, the polysilicon layer, the first nitride layer and the pad oxide layer to expose a portion of the underlying substrate. A field oxide region is then formed in the opening.

Abstract: A windshield wiper system in which a dedicated microcontroller controls not only the wiper motor, but also a solenoid which provides dynamically variable downforce on the wiper blade.

Abstract: According to the present invention, an integrated regulator having an adjustable reset threshold is disclosed. The integrated regulator has the following elements contained within an integrated circuit device: a transistor, a voltage reference block, an internal resistive network, an operational amplifier which regulates the voltage output signal of the integrated regulator by regulating the base current of the transistor, and a comparator which senses and communicates to the user when the operational amplifier is unable to maintain the voltage output signal within an acceptable range of a desired value of the voltage output signal. External to the integrated circuit device is an external resistive network. When the reset output signal of the integrated regulator is equal to an active state, this is indicative that the operational amplifier has been unsuccessful in keeping the voltage output signal within the acceptable range of the desired value of the voltage output signal, i.e.

Abstract: According to the present invention, a first memory block of the memory chip is placed into the long write test mode, meaning that all wordlines of the first memory block are turned off and the voltages on all the bitlines of the first memory block are controlled such that either all the bitlines true of a memory block are equal to a low logic level, all the bitlines complement of the memory block are equal to the low logic level, or all the bitlines true and bitlines complement of the memory block are both equal to the low logic level. Next, a second memory block of the memory chip is likewise placed into the long write test mode, while the first memory block remains in the long write test mode. After a long pause which causes a long write disturb condition, the memory blocks of the memory chip are one by one taken out of the long write test and read disturbed. Then, the rows of the first memory block are selected, one by one, in minimal cycle time to read disturb the first memory block.