Abstract: The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.

Abstract: A method for controlling writing for a tape recorder that is connected to a host and sequentially records, as a transaction, a plurality of records that are transferred from the host and stored in a buffer is provided, including receiving a synchronous command for a first transaction from the host; in response to the synchronous command, sequentially writing the plurality of records stored in the buffer to a tape as the first transaction; receiving the size of a second transaction following the first transaction from the host; calculating time for a backhitch associated with an operation of the synchronous command for the first transaction on the basis of the size; and performing the backhitch on the basis of the time for the backhitch.

Abstract: Selecting a destination tape recording device, out of a plurality of tape recording devices, for saving data. Particularly a technique for selecting a tape recording apparatus whose performance is optimal for data to be saved, thereby improving data backup performance in a plurality of tape recording apparatuses.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: A method for automatically identifying available storage components within a storage system, which are appropriate for storing consumer data in compliance with specified service level objectives (SLOs), including discovering available storage components; identifying and assigning service levels provided by each available storage component, wherein identifying and assigning service levels provided by each available storage component, includes classifying the available storage components based on their type of technology, and determining the SLO relevant capabilities of the available storage components; and storing resultant mapping of service levels to available storage components in a metadata repository.

Abstract: A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: An improved method of dicing a semiconductor wafer which substantially reduces or eliminates corrosion of copper-containing, aluminum bonding pads. The method involves continuously contacting the bonding pads with deionized water and an effective amount of a copper corrosion inhibiting agent, most preferably benzotriazole. Also disclosed, is an improved apparatus for dicing a wafer, in which a copper corrosion inhibiting agent is included in the cooling system for cooling the dicing blade.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: A keeper device design structure for dynamic logic used in integrated circuit designs includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.

Abstract: A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

Abstract: A method is provided for patterning a substrate. In such method a first mask, for example, a front-end-of-line (“FEOL”) mask is fabricated, the first mask including a plurality of first features such as FEOL features which are usable to pattern regular elements and redundancy elements of a substrate such as a microelectronic substrate and/or a micro-electromechanical substrate. The first mask is tested, i.e., inspected for defects in the features. Thereafter, a second sequentially used mask, for example, a back-end-of-line (“BEOL”) mask is fabricated which includes a plurality of second features, e.g., BEOL features, such features being usable to pattern a plurality of interconnections between individual ones of the regular elements and between the regular elements and the redundancy elements. The regular elements and the redundancy elements are patterned using the first mask and the interconnections between them are patterned using the second mask.

Abstract: A method and system to minimize the affects of thermal gradient distortion in reticles. A heat source and filter or filters are used to control which part or parts of the reticle receive additional radiation. The heat created by this additional radiation minimizes any thermal gradients across the mask by supplying a constant heat flux to the entire surface of the mask. The heat source can also be used to preheat the reticle to minimize any transient start-up effects.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded.

Abstract: A method for signal balancing across multiple random logic macros. The method inserts a programmable delay element into the design before the last buffer level on all signal paths. The random logic macro is then fully designed including cell placement and wiring. With programmable delay buffers in place, the random logic macros may be used within multiple designs, each having varying signal latency requirements.

Abstract: A method of producing a particle beam mask and mask structures to allow for the use of dummy fill shapes. This invention overcomes distortion in by adding a dummy shape in unexposed regions and applying a blocking layer to cover the dummy shape. The blocking layer is comprised of an aperture or additional mask mounted close to the mask or can be added to the mask itself.

Abstract: A mask structure and method of quantitatively measuring pellicle degradation in production photomasks by measuring overlay in test structures on the mask. A structure is located in a high transmission region close to a transition region between a low transmission and a high transmission region of the mask such that pellicle degradation impacts the printing of the object. A second structure is located in low transmission region such that the printing of the second structure overlaps the first and provides a measure of pellicle degradation.

Abstract: An electronic device carrier (110) adapted for transmitting high-frequency signals, including a circuitized substrate with a plurality of conductive layers (240a to 240g) insulated from each other, the conductive layers being arranged in a sequence from a first one of the conductive layers (240a) wherein a plurality of signal tracks (200) each one ending with a contact area (205) for transmitting a high-frequency signal are formed, and a reference structure (215a, 215b, 230) connectable to a reference voltage or ground for shielding the signal tracks the reference structure includes at least one reference track (230) formed in a second one of the conductive layers (240b) adjacent to the first conductive layer and at least one further reference track formed in one of the conductive layers (240d) different from the first and second conductive layer, a portion of each signal track excluding at least the area corresponding to the orthographic projection of associated contact area being superimposed in plan view t

Abstract: A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using worst case and best case signal latencies determines the average latency in each voltage domain. Then balancing signals at the other levels of the design by incrementing the latencies in each domain until a target level based on the slowest average latency is reached.

Abstract: A behavioral modeling technique that captures driver delay. The output characteristics of a typical driver are represented by two basic element types: switching and non-switching. Switching elements are functions of both time-varying and non-time-varying parameters, and non-switching elements are functions of non-time-varying parameters only. The outputs of these elements are characterized and tabulated by applying a DC voltage on the output of the driver and measuring the current through each element. The time-varying switching element are represent by time-controlled resistors. The invention provides a methodology to account for variations in input transition rate, supply voltage(s) or temperature.