Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip.

Abstract: A method and system for computing a supply chain planning process efficiency E in relation to manufacturing activities of an organization. Input data, including supply and demand input data, is received beginning at time T0. An iteration index R is set equal to 0. Then the method and system implements: incrementing R by 1; adjusting the input data (i.e., changing, deleting, or updating the input data); executing a central planning engine (CPE), using the input data; analyzing results of executing the CPE; and iterating, or computing and stopping. The iterating repeats the incrementing, adjusting, executing, and analyzing. The computing computes E. E may be a function of Q, C, and RP/T. Q is a manual edit ratio in conjunction with adjusting the input data, C=S/D, S is supply, D is demand, T=TE−T0, and P is a real number.

Abstract: Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

Abstract: Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.

Abstract: A method for synthesizing a logic circuit that is driven by a clock signal, and that has a plurality of clock domains each having a plurality of clock sinks. A semiconductor substrate is provided. All of the plurality of clock sinks of one clock domain are placed into at least one cluster of clock sinks on the semiconductor substrate. A clock sink-density of each cluster of clock sinks is approximately equal to or greater than a clock sink density of an integrated circuit. A first portion of the plurality of clock sinks of a domain have a higher sink density than a second portion of the plurality of clock sinks of the same domain. The first portion has a subregion and the second portion has a subregion. The subregion of the first portion is adjacent to the region of the second portion.

Abstract: The present invention provides various methods for eliminating printable alternating phase shift defects from an alternating phase shift mask without the need of using a trim mask. Specifically, unwanted printable defects are removed by employing methods which provide a gradual sloped region in the transparent or semi-transparent substrate which is formed in an area of the substrate opposite to that of the opaque image which is formed thereon.

Abstract: Disclosed is a method of designing voltage partitions in a package for a chip, comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.

Abstract: A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.

Abstract: A method of analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design. The method initially comprises providing a library of circuits for use in designing an integrated circuit chip and determining a supply current requirement and an operating voltage range for each circuit in the circuit library. The method then includes calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid, assigning regions of the power grid to each of the ports, and placing a set of circuits from the circuit library in regions on the power grid.

Abstract: A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.

Abstract: It is, therefore, an object of the present invention to provide a structure and method of blowing fuses in a semiconductor chip that includes creating a design for the chip using a library, generating test data from the design, extracting the fuse related information from the design to prepare a fuse blow table, building the chip with the design data, testing the chip to produce failed data, comparing the fuse blow table to the failed data to determine the fuse blow location data, and blowing the selected fuses based on the fuse blow location data. The extraction method can include creating a fuse map file based upon a correlation between physical pin locations on the chip and different fuse macros within the design, wherein an order of fuses within the fuse blow table matches an order of fuses within the fuse map file.

Abstract: An automated data processing system includes a relational database engine, storage devices having a database table, registry and binary large objects created and updated by the relational database engine and a user defined function engine retrieving data elements stored in the binary large objects. The registry includes data element classifications. The database table includes relational information of the data elements, the data element classifications and pointers to the binary large objects, and the relational database engine creates and updates the binary large objects based on the database table and the registry.

Abstract: Disclosed is a method of routing power from a power network to one or more power service terminals within a voltage island, comprising: dividing the power network into segments; creating power service terminal to segment connections based on a first set of criteria; removing selected power service terminal to segment connections based on a second set of criteria; and selecting one power service terminal to segment connection for each the power service terminal. The first criteria is includes power drop, wire length, wire size, wiring layer restrictions and the second criteria includes electro-migration, wire length and current criteria.

Abstract: A method and apparatus are provided for publishing part datasheets. A part characterization database is created, and the technical characteristics of parts in the database are ascertained. In addition to parts, part groups are created based on common technical characteristics of parts, and a database tree is created based on the technical characteristics of parts and part groups. A publishing interface coupled to the part characterization database is provided for coupling a publishing tool to the part characterization database so as to provide context to the technical characteristics of one or more parts characterized within the part characterization database. A computer program product also is provided for publishing part datasheets. The computer program product comprises means for creating the part characterization database, means for ascertaining the technical characteristics of parts in the database and means for creating part groups based on common technical characteristics of parts.

Abstract: A structure and method for performing a capacitance extraction on an integrated circuit, includes determining a parallel-plate capacitance between devices on different levels within the integrated circuit, adding extension shapes around each of the devices, reducing an area of overlapping extension shapes, multiplying a remaining area of the extension shapes by a constant to produce a fringe capacitance; and summing the parallel-plate capacitance and the fringe capacitance.

Abstract: A structure and method for improving yield during physical chip design comprises identifying non-critically timed minimum groundrule cells located within the chip design, determining if whitespace exists around the non-critically timed minimum groundrule cells, and replacing the non-critically timed minimum groundrule cells that have the whitespace with non-minimum groundrule cells if the replacing leaves a functionality of the circuit unaltered.

Abstract: A structure and method for evaluating an integrated circuit design includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the previous layer, removing database pointers for regions of the previous layer overlapped by the superseding layer, classifying the superseding layer and the previous layer as the previous layer, and repeating the method until all layers of the integrated circuit are evaluated.

Abstract: Increased write and erase tunnelling currents are developed by enhancement of an electric field near a floating gate with a shaped edge structure overlapping a source/drain diffusion and developing increased floating gate area with angled regions joined by edges in order to reduce write and erase cycle times. The edge structure is formed by selective and preferential etching in accordance with the crystal structure of a monocrystalline semiconductor substrate. The sharpness of the edges and concentration of the electric field may be enhanced by consumption and stress effects of oxidation of the substrate to form a floating gate insulator.

Abstract: A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.

Abstract: A structure and method of designing an integrated circuit includes generating at least one device shape, altering the device shape to comply with predetermined rules, forming a first hierarchical level abstraction around the device shape (where the first hierarchical level abstraction represents a perimeter of the device shape), preparing a first hierarchical level arrangement of first hierarchical level abstractions, altering the first hierarchical level arrangement to comply with the predetermined rules, forming a second hierarchical level abstraction around the first hierarchical level arrangement (where the second hierarchical level abstraction represents a perimeter of the first hierarchical level arrangement), preparing a second hierarchical level arrangement of second hierarchical level abstractions, and altering the second hierarchical level arrangement to comply with the predetermined rules.