Abstract: A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: A method and system for extracting circuit characteristics from a circuit design comprises extracting first cell characteristics from a portion of said circuit design using a first set of environmental conditions. The invention then extracts second cell characteristics from the portion of the circuit design using a second set of environmental conditions. The invention determines a difference between the first cell characteristics and the second cell characteristics and labels a placeability of the portion of the circuit design based on the difference.

Abstract: A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.

Abstract: A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated c

Abstract: A system and method for automatically creating testcases for design rule checking comprises first creating a table with a design rule number, a description, and the values from a design rule manual. Next, any design specific options are derived that affect the flow of the design rule checking, including back end of the line stack options. Then, the design rule values and any design specific options (including back end of the line stack options) are extracted into testcases. Next, the testcases are organized such that there is one library with a plurality of root cells, further comprising one root cell for checking all rules pertaining to the front end of the line, and another root cell for checking design specific options including back end of the line stack options. Finally, the DRC runset is run against the testcases to determine if the DRC runset provides for design rule checking.

Abstract: An exemplary embodiment of the invention is a method and system for determining a radius of curvature of a two-dimensional curved feature. The system includes an image acquisition device for obtaining images of said curved feature. A processor is coupled to the image acquisition device for receiving the images and converting the images to n sets of coordinates corresponding to points on the perimeter of the curved feature. The processor chooses at least three sets of said coordinates to define at least one group and fits each set of said coordinates from each group to an equation for a circle and determines a radius of curvature by solving each equation simultaneously. A storage device is coupled to the processor for storing processor data. An output device is coupled to the processor for outputting processor data.

Abstract: A system and method in a computing network for generating an integrated circuit (IC) tapeout file at a remote client workstation by transmitting prompted IC technical data to the mask manufacturer. The process validates that the tapeout file is complete and accurate prior to generating the final IC tapeout file to be archived in the mask manufacturer's database.

Abstract: A method of etching a substrate, includes measuring a reflectance signal from a reflective material deposited on the substrate as the substrate is being etched, correlating the substrate etch rate to the reflectance signal from the reflective material, and using the etch relation between the substrate and the reflective material to determine the etch target.

Abstract: A method for analyzing a gated clock design in which a disabling clock gating transition prevents an output transition from occurring, assuring that no clock glitching occurs. Delays and slews are computed so that the arrival time computation that includes clock and gate signal delays are computed at the output, providing tests which ensure that no glitch situation occurs. The delays and slews are computed using a static timing analysis, which includes situations such as a late and early arriving gate clock signals. The invention may be used in any static timing analysis test to ensure that a first transition on one input of a circuit prevents the propagation of a second transition on another input of the circuit.

Abstract: A method and structure for creating a photomask data set includes inputting a design data set, creating a simulated printed data set by applying a lithography simulation model to chosen levels of the design data set, merging each chosen level of the design data set with each corresponding level of the simulated printed data set in order to produce a merged design data set, applying at least one test to the merged design data set, correcting the design data set based on results of the test to produce a corrected design data set, repeating the creating of the simulated printed data, merging, applying the test and correcting using the corrected design data set until the corrected design data set passes the test, and outputting the corrected design data set as the photomask data set.

Abstract: This invention entails a data analysis system and method that was developed to specifically address the unique issues in understanding the capacity components of multi chamber systems. The analysis system expresses all components of capacity loss for all chambers in each tool in terms of a full tool equivalent (FTE). The analysis system measures how long the tool is available with only 1 chamber, 2 chambers, etc. working. It then combines that data with the WIP states to accurately determine the production, idle-no-WIP, idle-no-operator, and down components of a full tool.

Abstract: A method and structure for checking legality of books in a phase-shift circuit design mask which arranges the books in rows, determines a book polarity of phase shift mask features of each of the books, sums polarities of the books within each of the rows to produce a row polarity of phase shift mask features of the row, checks whether the row polarity complies with legal requirements of the circuit design, and modifies placement of the books until all of the rows comply with the legal requirements.

Abstract: A thin transition-metal based scattering layer of a mask blank for use in EPL systems is formed by providing the thin transition-metal scattering layer directly over membrane layers on a lot of substrates, thereby forming a continuous contact between the single transition metal-based scattering layer and the membrane layer. Preferably, the single transition metal-based scattering layer is a single tantalum-silicon composite scattering layer having a stoichiometry of TaxSi. The deposition parameters for depositing the thin transition-metal based scattering layer are adjusted to provide the scattering layer uniformly over all substrates within the lot. A first substrate from the lot of substrates is then selected, an initial stress measurement of the scattering layer is determined and then the substrate is annealed at a first temperature.

Abstract: This invention teaches a computerized method for diagnosing both transient and stuck faults in scan chains. The method first examines repeating patterns in the scan test to determine the type of fault and creates a signature load for each stuck and transient fault based on the pattern for each type of fault. The method then runs a simulation using the signature at a selected assumed fault position. The results of the simulation are then compared with the actual scan result to see if the fault position was determined. If not, the method continues to run simulation on selected assumed fault positions until the simulated result matches the actual scan test results.

Abstract: A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.

Abstract: A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.

Abstract: Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.

Abstract: A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.

Abstract: A method and structure for determining a range and a shape of a kernel function of a lithographic system which includes exposing, in the lithographic system, a photosensitive layer on a top surface of a substrate through a mask having a mask image, the mask image being of sufficient width to ensure a transferred image will not exhibit foreshortening but will exhibit corner rounding; developing the photosensitive layer to form the transferred image in the photosensitive layer; measuring a distance from an intersection of projected extensions of edges of the transferred image to a point along one edge where corner rounding starts; and defining the range of the kernel function as the measured distance. The projected extension edges are an unaltered version of the mask image overlaid on the transferred image and the foreshortening is a reduction in length of transferred images when compared to the mask image. Corner rounding occurs as a result of light diffraction and photosensitive layer development processes.