Abstract: A method and system for reducing particulate contamination of a photomask used in lithographic printing. A reticle assembly comprises a pellicle frame and membrane which is adhered to a reticle and encloses an air space over a photomask of the reticle. Particulate matter which can adversely affect a lithographic printing result can be present within the enclosed air space. According to the invention, an interior wall of the pellicle frame is provided with an adhesive surface, and the reticle assembly is subjected to a dislodging motion to dislodge the particulate matter on the photomask surface and cause it to be directed toward the adhesive surface of the interior wall and adhere thereto, removing this particular matter from the focal plane of the lithographic optics.

Abstract: A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

Abstract: A method and structure for forming subfield regions includes mechanical definition of the substrate through machining or mold forming. The subfield regions are filled with a sacrificial layer before the thin membranes are deposited. Slots are mechanically machined through a substrate (the slots have dimensions of membrane subfields) and filled with a sacrificial material. The substrate is planarized. A membrane material is deposited over the substrate and patterned. The sacrificial layer is then removed. A mold can be utilized to form the slotted substrate in place of the machining operation.

Abstract: A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.

Abstract: An assist feature is formed on a lithographic reticle or mask using a hybrid resist and an exposure dose such that only an annular area is effectively exposed having a width that is potentially less than the minimum feature size that can be resolved by the mask exposure tool to simultaneously or sequentially form both a feature of interest and an assist feature for enhancing imaging of the feature of interest when the feature is printed to a wafer. Since the assist feature can be imaged simultaneously with the feature of interest or multiple assist features imaged concurrently, possibly between closely spaced features, data volume and mask writing time are greatly reduced. The invention is particularly applicable to the scaling of contact holes for connections to active devices in extremely high density integrated circuits.

Abstract: A method for efficiently changing the embedded processor type in verification of system-on-chip (SOC) integrated circuit designs containing embedded processors. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. Typically, the embedded processor type changes as SOC designs change. However, changing the processor type may cause errors in verification due to the presence of processor-specific code distributed throughout the verification software. Thus, changing the processor type can entail a substantial re-write of the verification software. In the method according to the present invention, in verification software for verifying a SOC design including an embedded processor, processor-specific code is localized in a processor driver.

Abstract: A mask includes an in-situ information storage mechanism on the mask, which stores mask pattern data that is supplied to a microlithographic tool (e.g., an optical stepper). The advantages of using the invention include immediate availability of pattern data of a particular mask to the microlithographic tool for improved integrated circuit productivity.

Abstract: A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

Abstract: An automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprises adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.

Abstract: A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.

Abstract: A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.

Abstract: A method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level. The method comprises the steps of identifying a desired number of blocks for the second hierarchical level, representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary, and identifying transistor networks that extend across block boundaries. The method further comprises the steps of assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and re-assigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block. Preferably, the transistors are assigned from one block to another by identifying partitions for groups of transistors; and then reassigning assigning transistors on the basis of said partitions.

Abstract: Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.

Abstract: A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.

Abstract: A control target structure and method for monitoring the lithographic affects on minimum feature in a lithographic process. The control target uses line array elements having a nominal width. By changing the shape of the line-ends of the elements the control target can be optimized for controlling either focus or dose.

Abstract: A method for hierarchical layout of an electronic design using an electronic computer aided design system, wherein the method includes generating a parameterized pattern library and using an existing netlist and analyze in a pattern recognizer, from which a list of associations between the pattern library and the netlist is created. Renesting then occurs wherein the netlist using the list of associations is used for generating a hierarchical layout of the electronic components in the design.

Abstract: A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer.

Abstract: A method for communicating with and controlling design logic modules (“cores”) external to a system-on-chip (SOC) design during verification of the design uses verification software to generate and apply test cases to stimulate components of an SOC design in simulation; the results are observed and used to de-bug the design. Typically, SOC designs interface with cores that are external to the design. Existing methods of including such external cores in a verification test of a SOC design typically entail having to create special test cases to control the external cores; such test cases typically do not communicate with test cases being applied internally to the SOC and therefore lack realism. An external memory-mapped test device (EMMTD) according to the present invention is coupled between a SOC design being tested in simulation, and cores external to the SOC design.

Abstract: A phase shifting mask for use in lithographic processing of semiconductor substrates comprises a mask substrate substantially transparent to the energy beam used and a patterned phase shifting layer disposed on the mask substrate and having openings therein exposing the mask substrate. The patterned phase shifting layer is comprised of a material of differing composition than the mask substrate and is of thickness sufficient to shift the phase of an energy beam passing through the thickness of the patterned layer and the mask substrate by 180 degrees, compared to the phase of the energy beam passing through the phase shifting layer openings and the mask substrate. Preferably the phase shifting material is a siliconoxynitride and the substrate is quartz. The mask also includes a patterned layer of a material substantially opaque to the energy beam disposed on the mask substrate or the patterned phase shifting mask layer.

Abstract: The present invention provides a method and apparatus for processing instructions in which the time allowed for the execution of an instruction is dynamically allocated. The allocation of time for execution of instruction occurs after the instruction is sent to the execution unit. The execution unit determines whether it can complete the instruction during the current processor cycle. In response to an ability to complete the instruction within the current processor cycle, the execution unit issues a busy signal to the reservation station. The reservation station continues to hold the next instruction until the execution until is capable of processing it.