Abstract: A method for creating a guardband that incorporates statistical models for test environment, system environment, tester-to-system offset and reliability into a model and then processes a final guardband by factoring manufacturing process variation and quality against yield loss.

Abstract: A method and system for applying run rules on an individual part number basis in order to detect out-of-control events for a distinct sub-population within a general technology population. The invention thus provides for line tailoring by part number by acquiring measurement data of the part number from a manufacturing line for a measured parameter; retrieving a specification for the part number from a database; executing custom run rules by part number against the measured data using the specifications; and rejecting requests to process the part number if a run rule violation exists.

Abstract: A method, system and software for automatically generating a test environment for testing a plurality of devices (DUTs) under test in a test system. The multiple devices are tested by mapping the plurality of DUTs into pins of the tester system to create pin data; inputting into a test program generator pattern data, generic test program rules and the pin data; generating a multi-DUT test program and multi-DUT pattern data; and controlling the test system through the test program. The resulting fail data is then logged to each DUT.

Abstract: A mask structure and method of quantitatively measuring pellicle degradation in production photomasks by measuring overlay in test structures on the mask. A structure is located in a high transmission region close to a transition region between a low transmission and a high transmission region of the mask such that pellicle degradation impacts the printing of the object. A second structure is located in low transmission region such that the printing of the second structure overlaps the first and provides a measure of pellicle degradation.

Abstract: A method of reducing sound-induced vibrations in pellicles used in lithographic production of microelectronic features comprises providing a pellicle for protecting a photomask, monitoring background sound in the vicinity, or vibration, of the pellicle, providing opposing sound waves to the background sound, and causing the opposing sound waves to strike the pellicle to substantially cancel vibrations due to the background sound or vibration. When the background sound strikes the pellicle on one surface of the pellicle, the opposing sound waves may strike the pellicle on the opposing surface of the pellicle, and may be provided with substantially the same frequency and amplitude in the same phase to the background sound. Alternatively, opposing sound waves may strike the pellicle on the same surface of the pellicle as the background sound waves, may be provided with substantially the same frequency and amplitude in opposing phase to the background sound.

Abstract: A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.

Abstract: A method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.

Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Abstract: A system, method and program product for analyzing fabricator capacity. The invention simplifies analysis by determining a common tool set capacity based on common non-key shared tool sets, a technology capacity based on a unique tool set for a technology, and key shared tool set capacity. Capacity opportunities and constraints, and the capacity shortfalls of tool sets are then evident. Many potential fabricator wafer start loadings can quickly be assessed and the best candidates analyzed further by more detailed, but time-consuming methods.

Abstract: A system and method for reserving manufacturing capacity to satisfy a customer deliverable order for a product. The system and method uses a relational database tool adapted to receive said customer deliverable order; and a product manager tool operatively connected to said relational database tool, said product manager tool being adapted to obtain a block of part numbers from unallocated part numbers and to supply said block of part number to said relation database.

Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

Abstract: A process for manufacturing and a photomask including a chrome layer over a transparent substrate, followed by a thin hardmask/barrier layer directly over the chrome layer having a thin resist layer thereover. The thin resist layer is patterned and developed wherein the barrier layer acts to retard the formation of a resist “foot” at the bottom of the resist profile. Exposed portions of the hardmask/barrier layer and the underlying chrome layer are etched, and then any remaining hardmask/barrier layer and resist layer is subsequently removed by an etchant. The hardmask/barrier layer directly over the chrome layer enables an improved pattern transfer mask during chrome etching processes, allows for further reduction in the thickness of the resist layer, improves the image quality, the achievable minimum resolution features, and provides nominal image size control and image size uniformity across the photomask within current process flows and manufacturing.

Abstract: The current invention provides a method and apparatus that minimizes the destructive effects of non-reflected energy during lithography. More specifically, a cooling system is located within the mask. In one example, a cooling module is integrated into the EUV mask. The cooling module may be thermoelectric. The EUV mask comprises a substrate structure as a base for a reticle, a cooling layer, which is formed on the substrate structure and a planarizing layer deposited on the cooling layer. In another example, a cooling channel is formed within the mask.

Abstract: A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K+1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.

Abstract: Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria.

Abstract: The present invention divides a large graphics file into smaller “frames” of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

Abstract: An extreme ultraviolet lithography (EUVL) mask structure and associated method of formation. A first conductive layer is provided between a buffer layer and an absorber layer such that the buffer layer is on a multilayer stack. The multilayer stack is adapted to substantially reflect EUV radiation incident thereon. The absorber layer is adapted to absorb essentially all of EUV radiation incident thereon. A mask pattern is formed in the absorber layer. Formation of the mask pattern in the absorber layer is accompanied by inadvertent formation of a defect in the absorber layer. The defect is subsequently repaired. The mask pattern may be extended into the first conductive layer and into the buffer layer in a substantially defect-free process that exposes a portion of the multilayer stack. A second conductive layer may be provided on the absorber layer, wherein the mask pattern is also formed in the second conductive layer.

Abstract: A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

Abstract: A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.

Abstract: A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.