Abstract: A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.

Abstract: ROM cell programmed ON has N+ source implant spaced a given distance from the gate with LDD bridging the gap between the N+ source and the N channel. ROM cell programmed OFF has P+ implanted into this gap so as to completely override the LDD in this gap. The P+ prevents the N channel from forming ohmic connection to the N+ source.

Abstract: A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.

Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.

Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.

Abstract: A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.

Abstract: A high-speed differential-feedback cascode sense amplifier includes an output stage and a voltage clamp. The voltage clamp is coupled to a pair of bit-sense lines of a memory system or other sense line source. The output stage is coupled to the output of the voltage clamp for generating an output signal having a logic state determined according to the current difference across the bit-sense lines. The voltage clamp includes a pair of transistors (e.g., cascode transistors) in cascode to a differential-feedback gain stage. Bit-sense lines are coupled to the cascode transistors and the differential-feedback gain stage. The gain stage amplifies the current difference across the bit-sense lines to define feedback voltage signals input to the cascode transistors. The parasitic voltage difference across the bit-sense lines resulting from driving the cascode transistors is small, approximately 3-7 mV for an ECL sense amplifier.

Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Abstract: A BiCMOS input circuit which is capable of detecting signals below a particular range, such as ECL signals, is presented. The circuit is useful in conserving the number of pins in a BiCMOS integrated circuit in that a signal below normal ECL levels can trigger special functions, such as testing. The circuit has a plurality of CMOS inverter circuits connected in series with the input node of the first inverter connected to the input terminal of the circuit and the output node of the last inverter circuit connected to the output terminal of the circuit. Diode-connected bipolar transistor created a potential difference between V.sub.CC and the source electrode of PMOS transistor of each CMOS inverter circuit in a declining fashion from the first inverter to the last inverter. The last inverter circuit has no potential difference at all so that its output has a full CMOS swing.

Abstract: A membrane switch comprises an upper flexible layers, separation layer and a lower conductive layer mounted on a support. The membrane switch is designed to absorb the noise created when a key is depressed and an operating block collides with the layers directly beneath it. By creating several holes in the one or more of the lower layers of the membrane switch, and optionally the support that geometrically surrounds the aperture of the separation layer, the colliding force of the operating block on the laminated membrane switch is dispersed and much of the noise is absorbed.

Abstract: An ECL to CMOS translator for BiCMOS circuits. The circuit has a first bipolar transistor which switches the translator from a quiescent state to an active state in the presence of an ECL high level signal. An amplifier driving an NMOS capacitive load amplifies this signal to CMOS levels. Two clock signals reset the circuit to the quiescent state once the ECL high signal has passed. The circuit is kept in the quiescent state by a current source.

Abstract: A synchronous BiCMOS logic circuit which operates between two voltage supplies and has at least one input terminal, an intermediate node and an output terminal is disclosed. The logic circuit is capable of a high speed transition in response to a signal pulse from a first logic state to a second logic state at the input terminal. The logic circuit has at least one MOS input transistor of a first polarity having a gate electrode connected to the input terminal. The MOS input transistor is coupled between the first voltage supply and the output node by its source/drain electrodes. A first current supply connected to the output node to the second voltage supply and weakly holds the intermediate node low when the logic circuit is in an initial state with the MOS input transistor turned off.

Abstract: A Schottky diode is formed with a layer of intrinsic polysilicon separating a metal silicide layer from an n conductivity type active region. This structure avoids the necessity for a process step which opens a window in the intrinsic polysilicon layer and reduces the portion of surface area needed for formation of a Schottky diode, compared to previous devices. The Schottky diode can be formed as part of an overall process for forming an integrated circuit and can be positioned in parallel across the collector/base junction of a bipolar transistor to form a Schottky barrier diode-clamped transistor.

Abstract: A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits hgher packing density, and lowers buried layer-to-substrate capacitance.

Abstract: The present invention provides an ECL EPROM circuit which uses a MOS memory cell. The invention includes a technique for programming the memory cell using MOS voltage levels, and also includes circuitry for reading the memory cell at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components for reading the cell, while the writing path contains MOS components for programming and verifying the cell. The memory cell itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element.

Abstract: There is disclosed a static RAM cell and MOS device for making the cell along with a process for making the types of devices disclosed. The devices is an MOS device built in an isolated island of epitaxial silicon similar to bipolar device isolation islands, and has single level polysilicon with self-aligned silicide coating for source, drain and gate contacts such that no contact windows need be formed inside the isolation island to make contact with the transistor. The static RAM cell formed using this device uses extensions of the polysilicon contacts outside the isolation islands as shared nodes to implement the conventional cross coupling of various gates to drain and source electrodes of the other transistors in the flip flop. Similarly, extensions of various gate, source and drain contact electrodes are used as shared word lines, and shared Vcc and ground contacts.

Abstract: An improved lead for surface-mounted electronic components is described. The improved lead includes an opening through the portion of the lead to be placed in contact with the printed circuit board for soldering. The opening, having a diameter approximately equal to the thickness of the lead, enables the detection of correctly-soldered joints using automated inspection equipment. When the lead is correctly soldered, solder is drawn by capillary action into the opening where it forms a meniscus. By automatically detecting the curvature of the meniscus, the quality of the solder joint may be determined.

Abstract: The present invention provides for a sense amplifier having a pair of input nodes connected through isolating PMOS transistors to the differential input terminals of the amplifier. Each of the input nodes is also connected to the gates of a pair of carefully matched NMOS transistors and to the drain of the other of the matched pair. In addition, each of the input nodes is connected to the gate of one of two drive NMOS transistors. The drains of the drive NMOS transistors are each connected to the gates of two output PMOS transistors, the drains of which form the output terminals of the sense amplifier. The sources of the matched NMOS transistor pair are coupled to ground by a NMOS transistor and the sources of the drive NMOS transistors are coupled to ground by another NMOS transistor. When the differential signals at the input terminals are to be sensed and latched, the sources of matched transistor pair and the sources of the drive transistors are sequentially connected to ground.

Abstract: There is disclosed a process for making high performance bipolar and high performance MOS devices on the same integrated circuit die. The process comprises forming isoaltion islands of epitaxial silicon surrounded by field oxide and forming MOS transistors having polysilicon gates in some islands and forming bipolar transistors having polysilicon emitters in other islands. Insulating spacers are then formed around the edges of the polysilicon electrodes by anisotropically etching a layer of insulation material, usually thermally grown silicon dioxide covered with additional oxide deposited by CVD. A layer of refractory metal, preferably titanium covered with tungsten, is then deposited and heat treated at a temperature high enough to form only titanium disilicide to form silicide over the tops of the polysilicon electrodes and on top of the bases, sources and drains.