Abstract: A system for clipping polygons representing three-dimensional objects to produce a representation of the portion of the objects in a desired viewing space is disclosed. A guardband space at least partially enclosing the viewing space is defined. The polygons are compared to the guardband space to determine which polygons intersect at least one of the guardband planes defining the guardband space. The intersecting polygons are also compared to the viewing space to determine if they intersect at least one of the viewing planes defining the viewing space. Only polygons intersecting both a viewing plane and a guardband plane are clipped.

Abstract: A graphic processing system for representing three-dimensional objects on a monitor which uses a pipeline of polygon processors coupled in series. The three-dimensional objects are converted into a group of two-dimensional polygons. These polygons are then sorted to put them in scan line order, with each polygon having its position determined by the first scan line on which it appears. Before each scan line is processed, the descriptions of the polygons beginning on that scan line are sent into a pipeline of polygon processors. Each polygon processor accepts one of the polygon descriptions and stores it for comparison to the pixels of that scan line which are subsequently sent along the polygon processor pipeline. For each new scan line, polygons which are no longer covered are eliminated and new polygons are entered into the pipe. After each scan line is processed, the pixels can be sent directly to the CRT or can be stored in a frame buffer for later accessing.

Abstract: A silicide base shunt 50 and method of fabricating it are disclosed for a bipolar transistor. The base shunt 50 is fabricated using the first layer metal 36, 39 as a mask to etch silicon dioxide 27 surrounding the emitter 34 to thereby expose the underlying silicon epitaxial layer 24. Nickel or copper are then deposited onto the silicon 24 to form a region of silicide 50 extending from a base contact 36 to closely proximate the emitter 34, thereby minimizing the resistance of the extrinsic base region 24 of the transistor.

Abstract: A method and apparatus for controlling a parallel combination of correlation circuits which compare image pixels. A number of correlation circuits are provided, each having its own memory. The memories are loaded with image data with each memory being assigned a different block (region) of the image. Each memory is also loaded with an overlapping portion of an adjacent block so that a pattern can be stepped across the entire block, including a match of the first column of the pattern with the last column of the block. The loading is done by generating addresses corresponding to addresses for the source image with one or more of the most significant bits modified so that the address sequence received by the second and subsequent memories are identical to the address sequence received by the first memory. This allows the various blocks of the image in the different memories to be later simulataneously accessed in parallel using a single address sequence.

Abstract: Two pressure wheels are mounted on respective support parts and are pressed against respective edges of print medium by a common force-applying device such as a cable acting substantially equally on two mechanical devices on which the pressure wheels are mounted in order to transmit substantially identical forces thereto; each wheel may be mounted at one end of a lever which is hinged to the corresponding support part and which supports a pulley over which the cable passes.

Abstract: A biCMOS interface circuit receives a plurality of incoming signals at a first level and supplies a plurality of output signals at a second level. The interface circuit establishes control voltages which are used to maintain an identical trip point in each of a plurality of translator circuits. Generally, the trip point is set at midway between the "high" and the "low" levels of the incoming logic signal. The control voltages assure reliable performance over a wide operating environment.

Abstract: A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators.

Abstract: An expandable ECL matrix shifter is provided to have very few interconnecting wires. The shifter can perform a multicolumn right shift or a multicolumn left shift in one cycle, and it has independent wrap and fill capabilities. Two 2 to 1 multiplexers are provided for each bit position of the input signals. The input signals provide one of the inputs for both of the multiplexers. The second input of each multiplexer is a signal indicating what type of fill is desired. The shifter has horizontal data input lines, vertical data output lines, and diagonal select lines. A bipolar transistor is located at each intersection of a data input line and a data output line. These transistors selectively connect the data input lines to the data output lines in response to signals on the diagonal select lines. Each horizontal data input line is divided into two parts. The division of the data input lines into parts is along a major diagonal of the matrix.

Abstract: A network of filter elements for transforming an analog signal of infinite bandwidth into a discrete filter space representation having a bandwidth equal to .pi.. In one embodiment the filter network includes Laguerre filter elements. Other embodiments include methods for estimating the values of the amplitudes, frequencies, and phases of the frequency components of the analog signal, for reconstructing an input signal, and correcting for non-ideal filter elements.

Abstract: An improved method for the etch-back planarization of interlevel dielectric layers provides for cessation of the etch-back upon exposure of an indicator layer. the indicator layer, usually a metal, metal nitride, or silicon nitride is formed either within the dielectric or over an underlying metallization layer prior to patterning by conventional photolithographic techniques. A sacrificial layer, typically an organic photoresist, is then formed over the dielectric layer. Because of the presence of both relatively narrow and relatively broad features in the metallization, the thickness of the sacrificial layer will vary over features having different widths. As etch back planarization proceeds, the indicator layer which is first encountered releases detectable species into the planarization reactor. Detection of these species indicates that removal of the overlying dielectric layers to a predetermined depth is achieved.

Abstract: A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

Abstract: A system for determining the s-plane parameters, s.sub.i and r.sub.i, of the transient response, ##EQU1## of a network-under-test (NUT). A filter bank, including N serially connected filter elements, has an input port and N output ports being the output ports of the filter elements. The system includes circuitry for sampling the response signal, at the N filter bank output ports. T seconds after a transient signal is received at the input port. A processor utilizes the values of the sampled response signal to determine the values of s.sub.i and r.sub.i.

Abstract: A method for forming vertical metal interconnects on a semiconductor substrate having an uneven surface comprises first forming a laminated metal structure over the entire substrate. The laminated metal structure includes a first metallization sublayer, an intermediate etch stop barrier layer, and a second metallization sublayer. Usually, a barrier layer will be formed between the substrate and the laminated metal structure. The laminated metal structure is then patterned into the desired vertical metal interconnects, which interconnects are at different elevations because of the uneven underlying surface. The vertical metal interconnects are then planarized by first applying a dielectric layer and a sacrificial layer, etching back the combined dielectric and sacrificial layers to expose only the higher vertical metal interconnects, and then selectively etching back the second metal sublayer component of the higher vertical metal interconnects.

Abstract: A BiCMOS voltage reference generator circuit generates and maintains a reference voltage within 3 mV over an 80.degree. C. temperture range and over a 1 volt change in power supply level. The circuit uses feedback from the output of the reference voltage generator to the current source supplying current to the voltage reference generator. This feedback increases the effective output impedance of the current source, making the reference voltage output substantially independent of power supply variations. The circuit operates with power supply differential as low as about 3 volts, and preferably is fabricated from bipolar transistors and MOS transistors on the same chip.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: A video stream processing system comprising a novel modular family of image processing and pattern recognition submodules, the submodules utilize a unique system signalling and interface protocol, and thus can be cascaded and paralleled to produce complex special purpose image processing systems which can operate at video or near video data rates. A stream of digitized pixel data is pipelined through a variety of submodules to support a wide variety of image processing applications. A common video interface provides for handling pixel data in the video signal path and a processor interface allows communication to any modern microprocessor for overall system control, for optional addition image processing and for defining options within each submodule.

Abstract: A method for determining the transfer function of a data acquisition system involves inputting a set of bilevel input test patterns to the system and measuring the system's response. The input test patterns from a complete orthogonal set. The input test patterns or the system's response can be weighted to correct for aliasing error and/or to represent any arbitrary input waveform. From the ratio of the Fourier transform of the sum of the responses to the Fourier transform of the sum of the input test patterns the transfer function is derived. In operation, the transfer function is used to accurately determine the characteristics of any input waveform to the system.

Abstract: An instruction execution accelerator for a pipelined digital machine with virtual memory. The digital machine includes a pipelined processor which on memory accesses outputs a virtual address to a data cache unit (DCU). On particular memory accesses, such as store or similar operations, the pipelined processor can be advanced or accelerated to the next instruction once the memory access is known not to cause a page fault. The pipeline accelerator includes a small associative memory which the page number of a target address of a store operation is compared. If there is a match, it is know that the target address relates to a page within the real memory and the instruction can complete asynchronously. Otherwise if there is no match, the page address is inserted in the associative memory to become the most recent addition. On the recognition of a page fault by the DCU, the associative memory will be cleared to make room for the new entry and others.

Abstract: A bonding apparatus for eutectically bonding tape leads to semiconductors and other substrates includes four separate bonding rails for applying heat. The bonding rails have a preselected distribution of mass along their length in order to compensate for uneven heating characteristics which are normally observed in linear heating elements. Usually, four such heat elements are orthogonally arranged at the bottom ends of four electric power buses. By attaching the heating elements to adjacent power buses, and coupling diagonally opposed pairs of the power buses to the positive and negative polarity of a current source, substantially uniform heating of all four elements may be achieved. The ability to provide uniform heating is critical for properly forming eutectic bonds.

Abstract: A printer/plotter incorporates four individual microprocessor-based print stations, each for printing on a print media a separate color image for superimposition with one another, forming a final full-color image. The four print stations are located along a transport path for single-pass operation, and each print station includes a transport system that allows the media to traverse a print station with controlled forces exerted on the media by that station. The invention further includes a precise registration system wherein each print station monitors registration marks to detect variations of the media (i.e., stretching or shrinkage) during the printing process and to correct for such variations on obtaining accurate registration of the individual images for a full-color result.