Abstract: A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.

Abstract: A TTL/ECL translation circuit for translating TTL level input signals, which have a high voltage state and a low voltage state, to ECL level output signals, which have a high voltage state and a low voltage state. The translation circuit includes a TTL input circuit, a level shifter, and an ECL output circuit connected in series. The TTL input circuit receives the TTL level input signals and generates a first intermediate signal, corresponding to the TTL level input signals, that is transmitted to the level shifter. The level shifter receives the first intermediate signal and generates a second intermediate signal corresponding to the first intermediate signal that is transmitted to the ECL output circuit. The ECL output circuit receives the second intermediate signal and generates an ECL output signal corresponding to the second intermediate signal and the TTL input signal.

Abstract: A voltage is provided by a master circuit and received by a plurality of slave circuits over a bus. The master circuit includes a V.sub.bb reference circuit, a temperature compensation and V.sub.cse reference circuit, and a voltage step-up and buffering circuit coupled to the bus. Each of the slave circuits has a pair of transistors coupled to the bus in an emitter-follower configuration to step down the voltage from the master circuit and to provide a voltage reference. The voltage provided to the bus varies as it propagates through the bus. Accordingly, a plurality of unconnected resistors are formed in the portions of the silicon substrate which contain the master and/or slave circuits. When formed in the master circuit, the resistors are located in the V.sub.bb reference circuit. When formed in the slave circuit, the resistors are located in close proximity to the output transistors.

Abstract: A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from subsequent logic stages. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting part of the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

Abstract: A buried Schottky clamped transistor is described in which the Schottky diode comprises a region of metal silicide 24 in the epitaxial layer 15 adjacent the transistor. The structure includes an electrically isolated region of N type epitaxial silicon 15 having an upper surface, a region of metal silicide 24 formed in the epitaxial silicon 15 adjacent the upper surface, an emitter region 33 of first conductivity type also formed in the epitaxial silicon adjacent the upper surface, base region 29 of opposite conductivity type adjacent the upper surface which separates the emitter 33 from the metal silicide 24, and metal connections 37, 38 and 39 for making electrical connections to each of the regions of metal silicide 24, the emitter region 33, and the epitaxial silicon 15.

Abstract: A circuit is described for functioning as a transparent latch, a latch where the data is determined by the state of a data signal at the time a signal changes state, a D-type flip-flop, and a scan path element. The mode of operation of the circuit is determined by the condition of respective ones of a set of control signals.

Abstract: There is disclosed herein a base and emitter contact structure for a bipolar transistor which is comprised of a polysilicon stripe over an isolation island which stripe extends to a position external to the position of the isolation island and assumes the shape of an emitter contact pad. The emitter contact stripe has a layer of self aligned silicide formed thereover to lower its resistance, and this silicide is doped with both N and P type impurities one of which is selected to have a higher rate of diffusion than the other. A layer of self aligned insulating material is formed over the silicide and polysilicon of the emitter contact stripe. There are anisotropically etched insulating spacers formed on the sides of the emitter contact stripe, and there are silicide base contact stringers formed beside the spacers by anisotropic etching of a layer of doped silicide.

Abstract: A two-level 4:1 ECL multiplexer circuit comprising two 2:1 multiplexer circuits "OR'd" together prior to a shared output stage. A differential Select line, operable at the same voltage level as the input data lines to the 2:1 multiplexer circuits selects one of the input lines to each 2:1 multiplexer circuit. A second Select line, operable at a different voltage level, selects one or the other of the 2:1 multiplexer circuits. This arrangement functions to eliminate an undesirable glitch observed when selecting data inputs in known two-level, 4:1 multiplexers which use emitter dotting.

Abstract: A process which stores a representation of a polygon forming a portion of a three-dimensional object and compares the polygon to pixels from a scan line as they are passed by. The processor stores a representation of a polygon and compares each pixel passed by the processor to the polygon to determine whether the pixel is within the polygon. If the pixel is within the polygon, its Z position (depth) is compared to the Z position of a corresponding position in the polygon. If the Z position of the polygon position is in front of the Z position of the pixel so that the polygon would obscure the previous pixel description, the Z position and an associates material value (e.g., color) of the polygon is substituted for the Z position of the pixel. The three-dimensional object is preferably represented with triangles and each polygon processor is preferably a triangle processor, with a series of triangle processors arranged in a pipeline. Two pipelines may be provided in parallel.

Abstract: A custom bus for a visual signal (image) processing system which can interface with a standard high speed industrial standard computer bus and requires minimal interface circuitry. Eight lines are dedicated to eight data/address bits which are supplied to a bidirectional I/O buffer on each VSP circuit card. A separate board select signal is supplied to each circuit card to enable the I/O buffer. Six bits on six lines provided to each VSP circuit card provide a signal selecting a particular device on each circuit card. Each circuit card contains a decoding circuit for decoding the device select signal and enabling an individual device on the card in response to the device select signal.

Abstract: A process is disclosed for forming a planarized or smooth surface binary glass insulating film comprised of germanium dioxide and silicon dioxide by a spin-on process. The resulting structure has a film thickness uniformity which varies less than 5% over the surface of the wafer. The structure is formed by mixing a predetermined solution of TEOS and TEOG in a lower alcohol or ketone solvent and catalyzing by the addition of sufficient acid to raise the pH to 1.5 to 2.0 to favor gel formation. The resultant solution is then spun on at an RPM selected to give the desired film thickness for a given solids content of the solution.

Abstract: A circuit for providing a voltage reference level using a master circuit and a plurality of slave circuits. The master circuit includes a V.sub.bb reference circuit, a temperature compensation and V.sub.cse reference circuit, and a voltage step-up and buffering circuit. Each of the slave circuits has a pair of transistors in an emitter-follower configuration to step down the voltage and drive the circuitry requiring the voltage reference.

Abstract: A process for fabricating both bipolar and complementary field effect transistors in an integrated circuit is disclosed. The process begins with a structure having a P type substrate 10, an N type epitaxial layer 15, and an intervening N type buried layer 12. The process includes the steps of removing all of the epitaxial layer 15 and all of the buried layer 12 from regions of the substrate where NMOS devices are to be formed, to thereby leave second regions of the epitaxial layer 15 and buried layer 12 having sidewalls 21 protruding above the substrate 10. A layer of silicon dioxide 25 is formed at least over the sidewalls of the protruding regions, and then a further epitaxial deposition of silicon is employed to reform the epitaxial layer 28 over the first regions, which epitaxial layer 28 is separated from the previously formed epitaxial layer 15 by the silicon dioxide isolation 25. The process continues by fabricating bipolar and field effect transistors in separate ones of the first and second regions.

Abstract: An improved method and apparatus for classifying triangles. A description of a triangle in the form of the coordinates of its vertices is supplied to calculation logic. The calculation logic calculates a plurality or parameters of the triangle from these coordinates. These parameters are then provided to a look-up table. The look-up table has previously been programmed to include at each address the proper triangle classification for that address, with each address being a different combination of the parameters. The addresses for the look-up table cover all possible combinations of the parameters, and thus all possible triangles.

Abstract: A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.

Abstract: A method for directly measuring the area of a topological surface with an arbitrary boundary shape lying in a fixed elevation different from a fixed surrounding surface elevation relies upon binocular stereo vision. Three stereo correlation measurements are made, one over a window entirely within the surface of interest, a second over a window outside the surface of interest and within the surrounding area, and a third over a window fully containing the surface of interest as well as some of the surrounding area. The correlation measured in the third case is the linear sum of the correlation value over each of the first two cases weighted by the proportion of the window that the two surfaces occupy.

Abstract: A Schottky diode is fabricated according to the following steps: forming a layer of metal-silicide on an underlying dielectric layer, forming a polysilicon layer on the upper surface of the metal-silicide layer, forming a second dielectric layer on the upper surface of the polysilicon layer and patterning the second dielectric layer to create a contact window through the second dielectric layer to an exposed surface region of the polysilicon layer, and forming a metal contact to the exposed surface region.

Abstract: A force or pressure sensor includes a monocrystalline silicon diaphragm coated with silicon dioxide upon which single crystalline silicon resistors are fused in a low profile pattern on the surface. The resistors are almost perfectly electrically isolated from each other and from the underlying silicon substrate. The structure is fabricated by forming resistors in a first wafer and then affixing that surface of the first wafer to the silicon dioxide layer on the second wafer. All of the first wafer except for the resistors has been removed, and metal contact capable of resisting elevated temperatures are formed to provide electrical connections to the resistors.

Abstract: An improved Schottky barrier diode for increasing the alpha particle resistance of static random access memories includes an extra implanted N-type region at the surface of the epitaxial layer to increase the impurity concentration there to about 1.times.10.sup.19 atoms per cubic centimeter. In one device, arsenic is employed to overcompensate a guard ring where the Schottky diode is to be formed, while in another device phosphorus is employed and the guard ring is not overcompensated. The resulting Schottky diodes, when employed in the static random access memory cells, dramatically increase the alpha particle resistance of such cells, while also substantially decreasing the access time.

Abstract: A system is provided for application of a lighting model to a rasterized stream of pixels. The system typically includes a series of circuits, each for applying a lighting model to a single pixel. Each chip typically includes some memory sources for storing the lighting model, an input section connected to receive data indicative of the normal vector, Z depth, and material characteristics of the object represented by the pixel to be colored. A special purpose processor connected to the input then applies the lighting model to the pixel and supplies color value of the pixel as an output signal.