Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: An image processing system includes a synchronization separator 20 which operates to separate the synchronization pulses from the analog video information supplied. The separator includes an amplifier with a pair of input terminals. The video is coupled to one of the input terminals and a feedback loop coupled between an output terminal and the other input terminal. In this manner the negative synchronization pulses may be amplified while the positive video signals are limited. The extracted sync signal is used to control an analog-to-digital converter 70. The analog video information is then converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator 100, including a programmable delay line 300, which receives synchronization pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format.

Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.

Abstract: A fabrication process for integrated circuits having linear bipolar transistors and other circuit elements. The process defines collector contact 32, base 34, and isolation 36 regions in one masking operation. Subsequent masking layers of photoresist 40, 42, 46 are used to shield selected regions during implantation of exposed regions. Circuit density is improved through the use of aluminum doped isolation regions 36. The base region is doped in a single ion implantation step, which is followed by low temperature deposition of a covering oxide layer 48.

Abstract: A high speed voltage comparator circuit is disclosed which accepts a wide range of input potentials CBO1 and compares them with four potential levels CRH, CRL, CRIH, and CRIL. Each comparator includes input transistors Q103 and Q104, one of which is connected to the reference potential and the other is connected to the unknown potential. The emitters of the input transistors Q103 and Q104 are connected together through a resistor R105, and each emitter is connected to a current source, Q105 and Q107 respectively. A third current source Q106 is coupled to diodes D101 and D102 which are connected to the emitters of transistors Q103 and Q104 respectively. The difference between the reference potential and the unknown potential will forward bias one of the diodes and reverse bias the other. The resulting difference in emitter current between the input transistors Q103 and Q104 is detected by an output stage to indicate the relative magnitudes of the reference potential and the unknown potential.

Abstract: A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Programmable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing.

Abstract: A method for producing an improved capacitor in MOS technology utilizing a thin layer oxide dielectric to improve the active/parasitic capacitance ratio while maintaining a high breakdown voltage and a low leakage current.A polycrystalline silicon layer is formed over a silicon dioxide field region on a wafer of semiconductor silicon. Phosphorus ions are implanted in the polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV. The surface of the polycrystalline silicon layer is oxidized to form an interpoly oxide, utilizing an oxidation temperature which, for the implant dosage of phosphorus ions used, is sufficient to make the interpoly oxide layer approximately 770 Angstroms thick. The structure is then annealed at a temperature of approximately 1100.degree. C. in oxygen and HCl. A second polycrystalline silicon layer is formed over the interpoly oxide layer, and the process completed in the conventional manner.

Abstract: A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested.

Abstract: A formatting circuit for a high speed integrated circuit test system controls the application of timed data pulses to the input terminals of the device being tested, generates strobe signals to control comparators connected to the output terminals of the device being tested, and provides circuitry to decode error signals received from the device being tested. The formatting circuit routes all critical signal paths to the device under test over separate signal lines, thereby allowing compensation for the different propagation delay of each signal path. The input transitions and output strobe signals for the device being tested are not fixed in time with respect to the system clock, but are referenced to it. This enables drive data cycles and compare data cycles to be less dependent on the system clock, and permits them to overlap and cross test period boundaries.

Abstract: A plurality of test signal applying and response signal monitoring circuits is coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and response signal monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative magnitude of the response signal with respect to a programmed reference level on a repetitive basis during testing to increase test rate. Other features are also disclosed.

Abstract: A color image processing system is described which provides more realistic hard copy color images from composite video system input signals than previously available. The analog video information is converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator (100). The time base generator (100) provides more accurate control over the converter than the system clock signal. The generator (100) receives pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format. The generator (100) employs a delay line (300) to detect the fraction of a system clock period between the sync pulse and the next clock pulse. The specified number of clock pulses are allowed to elapse. Then the delay line (300) is used to provide the necessary further delay.

Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors Q1 and Q2 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: The two transistors of a bipolar flip-flop structure are interconnected by using a polycrystalline silicon/metal silicide sandwich structure. The polycrystalline silicon is doped to correspond to the underlying regions of the transistor structures, and undesired PN junctions created thereby are eliminated by depositing refractory metal silicide on the upper surface of the polycrystalline silicon.

Abstract: A programmable charge coupled device transversal filter 5 includes a charge coupled device register 10 for receiving and delaying incoming analog signals, a series of floating gate charge detectors 15, a corresponding number of sets of binary scaled capacitors C.sub.0, . . . 2C.sub.0 . . . 2.sup.n C.sub.0, an output circuit including a positive and negative bus coupled to a differential amplifier, and mask or otherwise definable electrical connections for connecting selected ones of the scaled sets of capacitors between the floating gate 15 corresponding to that set and one of the positive and negative buses 22 and 23.

Abstract: A high voltage analog solid state switch is disclosed which includes a pair of MOS FET's 10 and 20 having commonly coupled sources 11 and 21 and commonly coupled gates 13 and 23. A photovoltaic generator 30 and an opto-coupler 40 are connected in parallel between the commonly coupled gates and sources. The input node is connected to the drain of one transistor 10 while an output node is connected to the drain of the other transistor 20. The switch is turned on by application of light 32 to generator 30 to thereby positively bias the gates 13 and 23 and cause transistors 10 and 20 to conduct. The switch is turned off by application of light 42 to coupler 40 to thereby short the commonly coupled sources 11 and 21 to the commonly coupled gates 13 and 23.

Abstract: A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.

Abstract: An automatic test system for parallel loading of data into pin registers 100 associated with pins of a device being tested includes data bus 130 for transmitting data; an address bus 120 for transmitting addresses; a set of pin registers 100, each having a unique address and each coupled to receive information from the data bus 130; a participate register 150 coupled to data bus 130 and to each of registers 100 for enabling selected ones of registers 100 to receive data from the data bus at the same time; an address decoder 110, 180 connected to the address bus 120, to each of registers 100, and to the participate register 150, for enabling one of the pin registers 100 or the participate register 150 to receive data from the data bus, the data for the participate register 150 comprising the addresses of each of the selected ones of pin registers 100 which are to receive data from the data bus in parallel.

Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.

Abstract: A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current I.sub.D along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differential amplifier; and includes a second differentialamplifier for steering current I.sub.D along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential amplifier. An output stage produces a selected logic output signal according to which of said first and second current paths is selected to steer current I.sub.D. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers.