Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.

Abstract: A plastic semiconductor package suitable for high frequency operation includes an internal ground plane connected to a ground ring formed on the packaged semiconductor device. The ground plane is included as a portion of a lead frame strip adjacent to the individual lead frames. The ground plane is first folded underneath the paddle support of the lead frame, and the semiconductor die subsequently mounted on the paddle. The ground plane includes a plurality of bumps which protect upward between adjacent lead fingers of the lead frame when the ground frame is folded. A ground frame on the semiconductor die is connected to the bumps, and the signal bonding pads connected to the lead fingers, typically by wire or tape bonding. The package is then encapsulated in plastic by conventional means, and the package trimmed to its final desired configuration.

Abstract: An image processing system for computing morphological characteristics of object regions in a binary image frame. The characteristics are generated at the frame rate. One embodiment utilizes an architecture including an interconnected delay component, bit packing component and LUT. The output values provided by the LUT are accumulated over one frame cycle to compute morphological characteristics.

Abstract: A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

Abstract: There is disclosed a high performance MOS transistor structure of either the N channel or P channel variety and a high performance bipolar transistor structure. A process is disclosed which can make high performance CMOS and high performance bipolar devices on the same die.

Abstract: A method of fabricating polycrystalline silicon resistors having nearly zero or positive temperature coefficient includes the steps of depositing a layer of polycrystalline silicon, implanting the layer with silicon to make the layer substantially amorphous, introducing an impurity to dope the layer, and annealing the layer.

Abstract: A deglitching network for digital logic circuits includes a voltage actuated current source coupled to a linear tracking, constant voltage column clamp circuit. The deglitching network threshold level tracks closely with the predetermined voltage of the column clamp, which also acts as a current sink. When heavy current loads are switched from the column clamp and its voltage falls briefly, the deglitching network is actuated to inject current into the column clamp circuit and restore the preset voltage.

Abstract: A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a video camera. The processing of a frame of image data by each circuit component is simulated and the resulting frames of image data are stored until they are no longer needed by other components. The output of the simulated circuit is displayed on a monitor.The timing of the circuit is analyzed for distinct groups of components which must operate in synchronism. Scaling factors are calculated for each net in the group from the incremental scaling rate of each component and the connectivity of the circuit. The scaling factors indicate the relative rate at which value pixels arrive at each net. The time at which a reference pixel arrives at each net is then computed to ensure that corresponding pixels arrive together at components with multiple inputs.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: An arithmetic logic system for performing a variety of arithmetic and logical functions on pixel input streams such as averaging down the input image stream, computation of absolute values, and signed or unsigned, clipped or unclipped, addition, subtraction and multiplication. The arithmetic logic system has a first arithmetic logic unit connected to a plurality of input signals. A second arithmetic logic unit is coupled to the first arithmetic logic unit and operates on the output of the first arithmetic logic unit. A control unit is coupled to the first and second arithmetic logic units and controls the operation of the second arithmetic logic unit based on the output of the first arithmetic logic unit.

Abstract: An image sensor is disclosed which is capable of handling large amounts of signal charge with small shift registers. The image sensor includes photoelements 10 in which charge is accumulated in response to sensed conditions; electrically-controllable transfer gates 20 adjacent the photoelements 10 for controllably releasing the charge from the photoelements; vertical shift registers 30, separated from the photoelements 10 by the transfer gates 20, for receiving the charge from the photoelements, and a scan generator connected to the barrier 20 for supplying a series of pulses thereto, a group of pulses being required to release all of the charge accumulated in the photoelements 10.

Abstract: A process for signal matching. The process is general and can be applied to matching signals of arbitrary dimension. To implement the process, a suitable discretized description of the two signals to be matched is defined. Such descriptions can be the local signal extrema or any other qualitative signal significant points of interest or features. Allowable feature matches and values for matches are defined, and determined for all potential matches. Matches are confined to the features within defined matching windows and are mapped for each significant point. Within a defined similarity disparity window, a neighborhood of potentially interacting matches are evaluated. Matches within a neighborhood contribute to the decision about the appropriate match for each significant point to determine a composite similarity weighted best value match for each point. Mapping is piecewise continuous. The two signals are matched with disparities therebetween resolved and removed responsive to the best match values.

Abstract: A subsystem component for use in an image processing system to compute a gray scale histogram function or various statistical functions relating to the coordinates of a region or regions in a binary image. A selected function is computed at the video rate of frame generation.

Abstract: A high precision digital to analog converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compenate for errors of any bit combination. In a specific embodiment employing feedforward compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A method for determining the position of media in a system where images are applied to the media at subsequent stations includes the steps of placing on the media at a first position tracking information consisting of a pattern of electrostatic charge to provide information with regard to the alignment of the media at the first station, and at the second station detecting the pattern of electrostatic charge to determine the alignment of the media at the second station. Typically the media consists of electrostatic paper and the step of placing charge on the paper is achieved by positioning positively charged styli in close proximity to the surface of the paper.

Abstract: A sensitive deflector beam having an integral deflectable element utilizes an immobilization pin and a limit pin to prevent damage to the deflectable element during fabrication and use. The immobilization pin is inserted through the beam and to the deflectable element to hold the element rigidly in place during fabrication. Thus, relatively rigorous operations such as polishing and circuit deposition may be accomplished without damage to the element.

Abstract: A color printer/plotter includes a frame having a paper inlet, a number of print stations, and a paper outlet. The paper is pulled past the print stations by a single driver at the paper outlet. Each print station includes a electrostatic charging head having a flat charging surface against which a first roller, typically having a foam outer surface, presses with the paper therebetween. Immediately downstream of the charging head a toner roller supplies toner to the paper, the toner adhering to the charged areas on the paper. A second pressure roller presses the paper against the toner roller. The second pressure roller is offset slightly upstream of the center of the toner roller to aid toner roller-paper contact. The sizing and positioning of the toner and second pressure rollers is such so as not to significantly deflect the paper from the substantially straight paper path between the paper inlet and paper outlet.

Abstract: A bipolar/CMOS process includes bipolar transistors having emitters formed in less than a minimal masking dimension. An opening is formed through a polycrystalline silicon layer deposited on a silicon substrate. After coating the sides of the opening with silicon dioxide, the intrinsic base region of the bipolar transistor and the emitter region are implanted. The extrinsic base is formed by outdiffusion from the polycrystalline silicon layer. The structure includes an epitaxial layer which is more strongly doped below its surface than at its surface to enhance the performance of CMOS transistors formed therein. Additionally, the bipolar and complementary MOS transistors are self-aligned to each other by the manner in which the buried layers are formed.

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process enables distinguishing the bipolar devices from the CMOS devices with a single base mask 108, while requiring only a single additional mask 114 to define the bipolar emitter and MOS gates. The process forms the gate oxide 100 for the MOS devices at an early stage, then protects that oxide with polysilicon 103 during subsequent fabrication steps. Self-aligned metal silicide contacts 137 are separated from undesired regions using sidewall oxidation techniques.

Abstract: A color image processing system is described which provides more realistic hard copy color images from composite video system input signals than previously available. The image processing system includes a synchronization separator 20 which operates to separate the synchronization pulses from the analog video information supplied to it. The analog video information is then converted to digital form by an analog-to-digital converter. The converter operates under control of a time base generator 100, including a programmable delay line 300, which receives synchronization pulses from the synchronization separator, and following a programmable time delay supplies a control pulse to the converter to cause it to sample the analog waveform and convert it to digital format. Once the signal is digitized, it is converted from an additive color system to a subtractive one end enhanced before being supplied to the color plotter 8.