Abstract: In an electronic system (100), a regulator (200) couples a supply device (110) to a consuming device (120) through a series switch (210) and provides output current I.sub.OUT. A shunt switch (220) is provided across the output. Fast changes of I.sub.OUT due to switching on and off the consuming device (120) are accommodated by the regulator (200). The regulator (200) has a voltage divider (250, 260) to measure V.sub.OUT. Operational amplifiers (230 and 240') control transistors (210, 220) with different switching thresholds, They compare a measurement voltage V.sub.M derived from V.sub.OUT to a reference voltage V.sub.REF. When the consuming device (120) is switched off, the first amplifier (230) makes the series transistor (210) non-conductive; and then the second amplifier (240') makes the shunt transistor (220) conductive for a short time. Capacitance at the output node (205) is substantially discharged. After overshooting, the voltage V.sub.OUT returns to its previous value. Unwanted undershooting of V.

Abstract: In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.

Abstract: A differential amplifier (10) receives a differential input signal (V.sub.IN). The input signal is attenuated by a first attenuator (12) and applied to a tan h amplifier (16). The input signal is also attenuated by a second attenuator (14) and applied to a sin h amplifier (18). The input signals to the tan h amplifier and sin h amplifier are independently attenuated. The transfer functions of the tan h amplifier and the sin h amplifier each have a linear region and a non-linear region. The output of the tan h amplifier and the sin h amplifier are summed (26) so that the non-linear region of the tan h amplifier cancels with the non-linear region of the sin h amplifier. The overall transfer function of the differential amplifier is linear over a wide range of input signal amplitudes by the cancellation of the non-linear regions.

Abstract: A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514).

Abstract: A laterally formed bipolar transistor receives independent base biasing at a base terminal and gate biasing at a gate terminal for providing high forward current gain and improved frequency response. The collector and emitter are formed with a first conductivity type and disposed in a well having a second conductivity type. The gate of the lateral transistor is formed adjacent to the well between the collector and emitter and receives the gate bias. The base of the lateral transistor is formed adjacent to the well and receiving the base bias. The combination of independent base and gate biasing provides more mobile carries to improve the forward current gain and frequency response of the lateral transistor while reducing its overall area.

Abstract: A circuit and method control the common-mode potential at an output (17, 18) of a fully differential amplifier (32) by feeding forward a common-mode correction signal through the amplifier. An input signal (V.sub.IN+ -V.sub.IN-) is amplified in the amplifier to produce a differential output signal (V.sub.O- -V.sub.O+) at the output. A common potential of the differential inputs (37, 38) of the amplifier is sensed with a transistor (54, 56) biased to a reference voltage (V.sub.CM) and amplified through the amplifier to produce a common-mode correction signal to offset a common-mode component of the differential output signal. A feedback circuit (33-36) is used to develop the common potential from the common-mode component.

Abstract: A method and circuit (20) for reducing flicker. Pixel values (Y.sub.0, Y.sub.1, Y.sub.-1) are transmitted to input terminals (23, 21, 22) of the circuit (20). A first difference magnitude is calculated by subtracting the pixel value (Y.sub.0) of a middle pixel from the pixel value (Y.sub.-1) of an upper pixel and taking an absolute value of the result. A second pixel magnitude is calculated by subtracting the pixel value (Y.sub.0) of the middle pixel from the pixel value of a lower pixel and taking an absolute value of the result. A larger of the first and second pixel magnitudes is compared to a user-selected threshold value. The pixel value (Y.sub.0) of the middle pixel is either changed or left unchanged in accordance with the results of the comparison.

Abstract: A data receiver is arranged to receive data comprising a sync word having a predetermined data frequency (f.sub.tx) and predetermined value. A clock signal (SCLK) is generated which is substantially synchronised with the received data. The n clocks (CLK1-CLK8) are generated, each of the n clocks having a frequency (fclk) which is substantially the predetermined data frequency (f.sub.tx) and is out of phase with an adjacent clock of the n clocks by 1/n of a clock period. The sync word is sampled using each of the n clocks to determine which one of the n clocks is optimally synchronised with the sync word and to provide the determined one of the n clocks at an output (18). The determined one of the n clocks provides the clock signal (SCLK).

Abstract: An oscillating circuit includes a low power inverting amplifier (10) having an input (208) and an output (209) and having a relatively high resistance d.c. biasing path (2) associated therewith. A relatively low resistance path (3) can be switched so as to couple the amplifier input (208) and output (209) together during a bias settling phase of the circuit. A detector (50) detects the voltage at either the amplifier input (208) or the output (209) and switches the relatively low resistance path (3) so that it does not couple the input (208) and output (209) together when the detected voltage reaches a level just before a required operating voltage level.

Abstract: A computer implemented architectural design method for designing an integrated circuit. An algorithmic description of the behavior of the integrated circuit is created (step 202), from which a register transfer logic (RTL) implementation (400, 500) of the integrated circuit is generated by performing a set of design tasks (steps 204-212). The RTL implementation is modified after performing one of the design tasks by branching to another design task such that the design tasks are performed in any order. Data is stored in a common database (12) which can be edited interactively through one of a plurality of data editors (14-22).

Abstract: In a personal area network, a method for programming an appliance by a controller. The method includes steps of a) determining (358), by the controller (300), that the appliance (324) is included in the personal area network; b) determining (328), by the controller (300), that the appliance (324) is in data communication with the controller (300); and c) when the appliance (324) is in data communication with the controller (300), performing substeps of: i) requesting downloading (330) of a command set for controlling the appliance (324); ii) receiving (332) the command set for controlling the appliance (324); and iii) programming (401) the command set into a memory of the controller.

Abstract: A method (30) and apparatus (300) for characterizing the operation of an architectural system designed through a plurality of design tasks (102-112). The design tasks are associated with architectural design rules (114-124) that compare a mapping of the system to a set of rules which are indicative of an error-free system. Objects in the mapping that do not conform to the architectural rules are identified and can be displayed at multiple architectural levels through one or more editors (26-28) and modified without leaving the editors. The system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles. The annotated component (130) monitors states of the system for storing in an analysis database (24). States at selectable simulation cycles are displayed in different orders and at multiple architectural levels.

Abstract: A configurable semi-conductor integrated circuit has an area thereof formed with a plurality of logic circuits at discrete sites or cells respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones, each having a matrix array of cells, and further includes a porting arrangement for each zone; and a hierarchical routing resource structure including: (i) global connection paths having selectable connections with the porting arrangement of each zone and which extend continuously across more than one zone, (ii) medium connection paths extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths having for each cell a restricted signal translation system between inputs and outputs of the cells and defining first and second sets of logic circuits.

Abstract: An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Abstract: A circuit (28) and method of sensing data stored in a memory circuit provide a reference current (I.sub.REF) that tracks memory cell current (I.sub.BIT) over a range of temperatures and power supply voltages. A comparator circuit (66) senses the memory cell current with respect to the reference current to produce the stored data (V.sub.DATA) By sensing current rather than voltage, the voltage swing on a high capacitance bitline (39) can be reduced to improve speed. The reference current is set during testing of the circuit by applying programming voltages (V.sub.WELL, V.sub.CG, V.sub.BL) to a reference device (52) that matches a storage device (36) in the memory cell (30).

Abstract: A trench power switching transistor (10) is fabricated having sub-micron features on a body layer (26) without using sub-micron lithography. An opening in a field oxide layer (28) defines an area for implanting a source region (30) in the body layer (26) that is self-aligned to a first edge (28A) and a second edge (28B) of the field oxide layer (28). Sidewall spacers (32) are formed in accordance with the first and second edges (28A and 28B) of the field oxide layer (28). A trench is aligned to the sidewall spacers (32) and formed centered within the source region (30). An implant layer (42) formed between sections of the power switching transistor (10) is aligned to the sidewall spacers (32) at the first and second edges (28A and 28B).

Abstract: A ferroelectric memory array (20) monolithically integrated with a field programmable gate array (32) into a semiconductor circuit (10). The ferroelectric memory array (20) is suitable for a semiconductor manufacturer to program the configuration data that is used in the field programmable gate array (32) prior to shipment and installation in an electronic system. The memory array (20) provides the data that configures the field programmable gate array (32) for functionality of the Configurable Logic Blocks (CLBs) in the field programmable gate array (32). Should the field programmable gate array (32) circuit lose power, the non-volatile memory array (20) provides a shift register (26) with the data to reconfigure the field programmable gate array (32).

Abstract: A current limiting circuit (70) controls the leakage current of a memory circuit (24) of a portable wireless device (10) while operating in a standby mode. A first semiconductor well (64) isolates the memory circuit (24) that is disposed in a second semiconductor well (66) from a substrate (62). In the standby mode the current limiting circuit (70) is switched to a non-conduction mode that limits the leakage currents of a diode formed by the first semiconductor well (66) with the second semiconductor well (64) and a diode formed by the second semiconductor well (64) with the substrate (62).

Abstract: A semiconductor device (400) and method are provided for multiplying a capacitance. A contact region (402) is formed in an island in a semiconductor substrate (499) bounded by an isolation region (403), producing the capacitance at the junction of the contact region (402). A dielectric layer (404) is formed over the semiconductor substrate (499) adjacent to the contact region (402). A contact layer (408) is formed over the dielectric layer (404) wherein an inversion layer (406) is formed under the contact layer (408), producing an inversion capacitance in response to an enabling signal. The inversion capacitance corresponds to a multiple of the capacitance.

Abstract: A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).