Abstract: An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. The data transfer count corresponds to the amount of data transferred and the number of cycle in the data access phase. The data access phase begins by accessing the data register corresponding to the address from the command phase. During subsequent cycles of the data access phase, the external tester accesses sequential data registers. The programmable built-in self test unit includes a pointer register and an adder to update the address each cycle of the data phase.

Abstract: A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the device. A password for providing full communication in the data path is stored in a defined location in the memory. Upon reading the memory location, the password is provided to a code security module. The password provided to the code security module is compared to a data string provided by the user. If the password and the data string match, the password data path is open for communication between the memory and the processor core. If the password and data string do not match, the password data path is closed to communication between the memory and the processor core.

Abstract: A storage device performs error correction for all data read from media. Correctly read data or data that is corrected following the reading is transferred to a host for use. If the error correction fails, the storage device transfers a unique error code. The host distinguishes the received data between normal one and unique one. The normal data flows into main data handling routine and the unique code flows into error data handling routine. The processed results of both data are stored into system memory area in the host. The host controls the read out schedule and response to the unique code. This method can prevent the host breakdown from data trouble in the external storage device.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: A simple to implement sample rate conversion system consisting of an input/output data flow controller, interpolation coefficient generation, and output data flow control to generate the converted data stream. Sample rate conversion may be done at real time video rates, without restrictions on the conversion ratios.

Abstract: A method for arbitration grants access to an ultra high priority device if the ultra high priority device requests access. This access is limited to a selectable number of accesses. Thereafter the ultra high priority device is masked from requesting access for a selectable interval of time during which access may be granted to other devices. The number of assess and the interval of masking are preferably controlled by memory mapped data registers loaded into dedicated counters.

Abstract: A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite gate 251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

Abstract: A method for preamble detection in mobile unit to base unit wireless telephony sets a preamble detection threshold based upon a Beaulieu series computation dependent upon preamble correlation data. This preamble detection threshold adjusts for noise by assuming the noise is additive White Gaussian noise (AWGN) with a known variance. The method determines the threshold for achieving a probability of false detection of the preamble from noise input of less than 0.001.

Abstract: In-circuit-emulation of an integrated circuit includes a digital data processor capable of executing program instructions. A first debug event is detected during normal program execution. The causes the in-circuit-emulation to suspend program execution except for real time interrupts. A debug frame counter increments on each interrupt and decrements on each return from interrupt. If a debug event is detected during an interrupt service routine, that interrupt service routine is suspended and the count of the debug frame counter is stored. Execution of other interrupt service routines in response to corresponding interrupts is still permitted. The integrated circuit includes plural debug event detectors and the debug frame count is stored at the detector detecting a debug event during an interrupt service routine. This permits a determination of the order of interrupts triggering debug events by reading the stored debug frame count from each debug event detector.

Abstract: This invention is a method for inverse Wavelet transform using a breadth-first output data calculation which uses input data to calculate at least one output data for each iteration of a software loop even if the same input data is used in a later iteration for calculating other output data. This reduces data movement between memory and the data processor core thus reducing the possibility of cache misses and memory stalls due to access conflicts. The input data and computed output data are preferably stored as subwords packed within data words in memory. In inverse Wavelet transformation this method performs vertical spatial frequency expansion and horizontal spatial frequency expansion for each level of Wavelet encoding. This invention arranges data flow providing a more efficient use of memory bandwidth and cache space than other known methods.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: A computer system (10) and method are presented for performing ECC corrections on data contained in a mass data storage device (20). The computer system (10) has a host computer (12) having a CPU (14) and an associated mass data storage device (20). At least some ECC hardware is associated with the mass data storage device (25). A device driver (18) is associated with the host computer (12), which includes software instructions for execution by the CPU (14) for performing at least some ECC functions or instructions on data read from the mass data storage device (20).

Abstract: A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements operable to receive input signals. The microprogram memory includes a microprogram operable to control the datapath in order to process the input signals. The microcontroller is operable to modify the microprogram based on a modification command.

Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

Abstract: A method for arbitration among a plurality of requesting devices for a shared resource in which one device is an ultra high priority device grants access to one requesting device at a time. The ultra high priority device is granted access if it requests access interrupting access by another device. The ultra high priority device is limited to a selectable number of accesses and thereafter is masked for a selectable interval. This interval permits access may by other devices. Each of the other devices is also limited to a selectable number of accesses followed by re-arbitration. The other devices can have a normal priority or a time out priority if a request hasn't been granted in a selectable amount of time.

Abstract: The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.

Abstract: A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to store in a destination data register. The execution unit may zero extend or sign extend the remaining most significant bits of the destination data. In an alternative embodiment, the execution unit includes plural multiplexers, one for each section of the destination data. Each multiplexer received data from each section of the source data register or registers. Special codes in the sections of the second source data register may select 0 fill, 1 fill or sign extension from the next most significant section for each multiplexer.