Patents Represented by Attorney Robert D. Marshall, Jr.

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  • Video processing subsystem architecture
    Patent number: 7502075
    Abstract: A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: March 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: David E. Smith, Deependra Talla, Ching-Yu Hung
  • Tracing user change of program counter during stop event
    Patent number: 7502727
    Abstract: This invention tracks emulation changes in the program counter of the central processing unit of a data processor during emulation halt. The sequence includes: pausing the central processing unit in response to an emulation halt; employing the emulator to change the program counter. In this case when the central processing unit resumes operation, there will be a discontinuity in the program counter. The trace data will show a change in the program counter address. This invention uses a unique exception signal similar to those used to mark interrupts to inform the user that this program counter discontinuity is due to an emulation change of the program counter during emulation halt.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, Lewis Nardini, Timothy D. Anderson
  • Dynamic sound source and listener position based audio rendering
    Patent number: 7492915
    Abstract: This invention describes the use of dynamic sound source and listener position (DSSLP) based audio rendering to achieve high quality audio effects using only a moderate amount of increased audio processing. Instead of modeling the audio system based on sound and listener position only, the properties that determine the final sound are determined by the change in listener relative position from the current state and last state. This storage of the previous state allows for the calculation of audio effects generated by change in relative position between all sound sources and listener positions.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: February 17, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Steven R. Jahnke
  • Emulation cache access for tag view reads
    Patent number: 7487421
    Abstract: A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: February 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Ananthakrishnan Ramamurti
  • Cross-referencing cache line addresses with corresponding names
    Patent number: 7484053
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels. The caches comprise a plurality of cache line addresses, each cache line address associated with a corresponding name. The software causes the processor to display the information on a graphical user interface (GUI), the GUI cross-referencing each of the cache line addresses with a corresponding name.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: January 27, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Oliver P. Sohm, Brian Cruickshank
  • Unique pBIST features for advanced memory testing
    Patent number: 7475313
    Abstract: This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used in test in native form or in inverted form. Different built-in self test instructions update pointer including reset to the first bit, no change, increment to the next bit and decrement to the previous bit. For write instructions the selected normal or inverted data is written into memory. For read instructions the selected normal or inverted data is compared with data read from a memory.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: January 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Ananthakrishnan Ramamurti
  • Progressive extended compression mask for dynamic trace
    Patent number: 7475172
    Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: January 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Lewis Nardini, Manisha Agarwala, John M. Johnsen
  • Scan sequenced power-on initialization
    Patent number: 7469372
    Abstract: A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This technique supplies a predefined pattern to parallel scan chains following power-on reset. The predefined pattern places the device or module in a architecturally specified reset state. The parallel scan chains are required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: December 23, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Lewis Nardini, Alan D. Hales
  • Method for collaboration of issue-resolution by different projects in a processor design
    Patent number: 7464347
    Abstract: This invention is a toolset upgrading the basic WEBS system update that facilitates tracking design bugs. This invention provides an effective means for reporting, tracking, and eliminating design bugs in an environment of collaborating projects employing re-useable design hardware modules. This invention provides web-based bug reports and uses a tracking program with a SQL database to store all bugs. This invention allows bug reports sharing, alerting and tracking between many different projects.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: December 9, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francis C. Ngoh, Jayesh K. Tolia
  • Stalling CPU pipeline to prevent corruption in trace while maintaining coherency with asynchronous events
    Patent number: 7464018
    Abstract: A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: December 9, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, John M. Johnsen
  • Read FIFO scheduling for multiple streams while maintaining coherency
    Patent number: 7457739
    Abstract: A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: November 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, Maria B. H. Gill
  • Loop deblock filtering of block coded video in a very long instruction word processor
    Patent number: 7457362
    Abstract: This invention is applicable to filtering block artifacts of macroblock and block oriented video compression. This invention computes all possible filter results speculatively and simultaneously in parallel, computes conditions for application of corresponding filter results simultaneously in parallel, and writes filter results to memory conditionally dependent upon computed corresponding conditions. This invention permits effective block filtering on a very long instruction word data processor.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: November 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Jagadeesh Sankaran
  • Fast fourier transform operation with reduced cache penalty
    Patent number: 7454452
    Abstract: A data processing apparatus having data cache performs an N-point radix-R Fast Fourier Transform. If the data set is smaller than the data cache, the data processing apparatus performs the Fast Fourier Transform in logRN stages on all the data set in one pass. If the data set is larger than the data cache but smaller than R times the data cache, the data processing apparatus performs a first stage radix-R butterfly computation on all the input data producing R independent intermediate data sets. The data processing apparatus then successively performs second and all subsequent stage butterfly computations on each independent intermediate data set in turn producing corresponding output data. During the first stage radix-R butterfly computations, each of R continuous sets are separated in memory by memory locations equal to the size of a cache line.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: November 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Oliver P. Sohm
  • Area efficient serializer implementation for small functional-to-serial clock ratios
    Patent number: 7450616
    Abstract: This invention adds one extra bit which can be viewed as a shadow of most significant bit of the serial register. This extra register bit is referred as buffer_flop. When the receive data is coming in, the data bits keep shifting into the serial register of the serializer block bit by bit. The first bits enters into the most significant bit of the serial register and is shifted towards the least significant bit of the serial register. When a whole block of bits (32 bits) are received, the serializer is full and is read into the VBUS clock domain. The first bit of next block of bits is stored in the buffer flop. The second bit is stored in the most significant bit of the serializer and the buffer flop bit is copied into the second most significant bit of the serializer. Subsequent bits are received and right shifted by one.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: November 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Subash Chandar Govindarajan, Sanjay Tanaji Shinde
  • Method of leakage optimization in integrated circuit design
    Patent number: 7448009
    Abstract: This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells, identifies corresponding candidate cells having the same function and swaps a candidate design cell having a least leakage current for the design cell.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: November 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Shrikrishna Pundoor
  • Semiconductor device testing
    Patent number: 7446552
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: November 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Cano, Juan C. Martinez
  • Semiconductor device testing
    Patent number: 7446553
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: November 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Cano, Juan C. Martinez
  • Load balanced interrupt handling in an embedded symmetric multiprocessor system
    Patent number: 7444639
    Abstract: In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the interrupt and then passes information to the central processing unit scheduling software. This software will in turn determine which central processing unit can best handle the interrupt. Because the scheduling software is able to determine which central processing unit handles the interrupt process, it can maintain central processing unit load balancing resulting in better system performance.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: October 28, 2008
    Assignee: Texas Insturments Incorporated
    Inventor: Steven R. Jahnke
  • Tracing through reset
    Patent number: 7444504
    Abstract: A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: October 28, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Manisha Agarwala, Lewis Nardini
  • Determining the presence of a virtual address in a cache
    Patent number: 7444474
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from caches associated with different processor cores. The software also causes the processor to provide the information to a user of the software. The status information indicates whether one of the caches comprises an entry associated with a virtual address.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: October 28, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Oliver P. Sohm, Brian Cruickshank