Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: A method of context adaptive binary arithmetic coding and decoding groups a plurality N binary symbols in corresponding syntax elements and divides a range into 2N subranges based upon corresponding contexts. The invention encodes data by selecting an offset determined by the probability states of the context of the N binary symbols. Decoding is similar with the place of the coded offset within the 2N subranges determining the syntax decoding. When the total number of binary symbols to be coded does not equal an integral multiple of N, the invention codes dummy binary symbols at the end of a grouping of a plurality N binary symbols. Probability state updates occur only following every N binary symbols.

Abstract: A server for a merchant computer system, the server comprising: a file store for storing a range of audio/video products in respective product files; a dialogue unit having a network connection and operable to invite and receive a client selection from among the products via the network connection; a product reader for reading the product files to generate a digital audio/video signal; a digital signal processing unit having an input connectable to receive the digital audio/video signal from the product reader, a processing core operable to apply a defined level of content degradation to the digital audio/video signal, and an output connected to output the degraded digital audio/video signal from the processing core to the network connection. It is therefore possible for a content provider to change the characteristics of an audio or video data stream supplied over a network to a potential purchaser in a controlled and variable manner.

Abstract: A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is presented. Additionally, a method and apparatus for enabling the support of a variable number and type of time slots within a time division multiplexed serial protocol is presented.

Abstract: A method and apparatus for providing music information for a wireless CD player is disclosed. The CD player may transmit a substantially unique CD tag to a music information service computer system across a network via a wireless communications protocol. The music information service system then matches the CD tag to music data stored in a database. This music data is then transmitted to the CD player to be displayed to the user.

Abstract: Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor operates in one of a plurality of states wherein primary code may be executed by the processor depending on said state. Upon a reset being asserted the processor begins executing code for a reset routine. The processor also executes a process such that the processor operates in the same state it was in prior to the reset upon the reset no longer being asserted.

Abstract: This invention is a method for binaural localization using a cascade of resonators and anti-resonators to implement an HRTF (head-related transfer function). The spectrum of the cascade reproduces the magnitude spectrum of a desired HRTF. The proposed method provides a considerably more computationally efficient implementation of HRTF filters with no detectable deterioration of output quality while saving memory when storing a large quantity of HRTFs due to the parameterization of its resonators and anti-resonators. Finally, the method offers additional flexibility since the resonators and anti-resonators can be manipulated individually during the design process, making it possible to interpolate smoothly between HRTFs, reduce spectral coloring or achieve higher accuracy at perceptually relevant frequency regions. These HRTF are useful in stereo enhancement and multi-channel virtual surround simulation.

Abstract: During trace recording, on-chip trace export mechanisms may schedule output from multiple sources out of order of execution. This makes the exact arrival of trace information in the receiver imprecise. Time of the day or time stamp information may be placed in the trace stream itself to assure correct timing, and represented as a control word. This may be done periodically or at the first empty slot after some period has elapsed.

Abstract: An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generated on the basis of bit signals (a0-a15, b0-b15) for the portion from the 1st digit to the 15th digit of the input data, and of carry signal CIN input to the 1st digit, and it is output from CLA 204. Then, carry signal c15 from the 16th digit to the 17th digit is generated based on said generated carry signal c14 and bit signals (a15, b15) of the 16th digit of the input data, and this is output from CIA 205. Exclusive-NOR circuit 206 then operates on said carry signals c14 and c15, and overflow detection signal OVF16 is generated.

Abstract: A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted dynamically at runtime to optimize the performance of the interface.

Abstract: The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A control stage (CONTROL) received a clock selection signal (SEL) and provides multiplexer control signal (MUX_SEL). A change in multiplexer control signal (MUX_SEL) is triggered by a next edge of target clock (CLK1) following a delay. This prevents glitches in the output signal.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. Each of the caches comprises a plurality of cache lines, and each cache line is associated with a way. The software also causes the processor to reassign the way of a cache line to a different way.

Abstract: This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word data processor to prevent over-execution upon loop exit. The method replaces a register modifying instruction with an instruction conditional upon the inverse condition register if possible. The method inserts a conditional register move instruction to a previously unused register within the loop if possible without disturbing the schedule. Then a restoring instruction is added after the loop. Alternatively, both these two functions can be performed by a delayed register move instruction. Instruction insertion is into a previously unused instruction slot of an execute packet. These changes can be performed manually or automatically by the compiler.

Abstract: A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.

Abstract: This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A predetermined one of these instructions is used as a special header. This special header has a unique encoding different from any normal instruction. When decoded this special header instructs decode hardware to decode this fetch packet in a special way. In one embodiment a bit field in the header signals the decode hardware whether to decode each instruction word normally or in an alternative way. The header may include extension opcode bits corresponding to each of the other instruction slots. In another embodiment another bit field signals whether to decode an instruction field as one normal length instruction or as two half-length instructions.

Abstract: A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.

Abstract: An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.

Abstract: The problem of the invention is to improve S/N and provide a high-sensitivity imaging device. The CMOS image sensor includes multiple pixels arranged in a two-dimensional array, where each pixel includes a photodiode PD that receives light to produce charge, a capacitance element FD, and a transfer transistor M1 connected between photodiode PD and capacitance element FD, where the capacitance of capacitance element FD is less than the capacitance of photodiode PD. With the drive method, transfer transistor M1 turns on during a predetermined period in a first charge transfer mode after the charge accumulation period is completed; first charge Q1 accumulated on photodiode PD is transferred to capacitance element FD; the charge on capacitance element FD is then reset; transfer transistor M1 turns on during a predetermined period in a second charge transfer mode after reset is completed; and second charge Q2 accumulated on photodiode PD is transferred to transfer element FD.

Abstract: This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.

Abstract: A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical functional unit supplies its output to a pipeline register. A comparator and multiplexer select a register input for each functional unit or the output of a corresponding pipeline register dependent. In the preferred embodiment, each critical functional unit has a throughput delay time longer than the average of throughput delay times of all functional units.