Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
Abstract: In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.
Abstract: In one embodiment, a voltage regulator uses a first current to charge a by-pass capacitor for a first time period and uses a second current after the first time period.
Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.
Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
Abstract: A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.
Abstract: In one embodiment, a power supply controller is configured to reset or override a soft-start reference signal responsively to the output voltage decreasing to a value that is less than a desired regulated value of the output voltage.
Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
Type:
Grant
Filed:
February 6, 2007
Date of Patent:
November 17, 2009
Assignee:
Semiconductor Components Industries, Inc.
Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.
Abstract: A switching power supply controller includes a comparator to compare a feedback signal to a first limit and a second limit, one of which includes a ramp. Limit generators may be used to generate limit signals in response to power supply signals, control signals, and/or output signals. An error amplifier may be used to generate the feedback signal in response to an output signal and an input control signal. A switching power supply may alternatively include an oscillator that shifts the switching frequency in response to the input control signal.
Abstract: A switch drive circuit utilizes charge transfer within and/or between boost circuit and/or snubber circuits for boosted switch drives. A boost circuit may include a divider to limit a boosted signal for driving a switch. A snubber circuit may transfer charge to a boost circuit.
Abstract: In one embodiment, an error amplifier of a power supply controller is configured to receive a current sense signal prior to the current sense signal undergoing amplification.
Abstract: In one embodiment, a vertical N-channel transistor is coupled in a high side configuration to control a current through an LED. A control circuit operates the vertical N-channel transistor to control a value of the current.
Abstract: In one embodiment, a current regulator is configured to form a first signal representative of a current flow through a power switch and to use the first signal to determine an off-time of the power switch.
Abstract: In one embodiment, a reference generator forms a reference signal that may have temperature and process variations. A comparator that has similar variations is used to detect a signal using the reference.
Abstract: In one embodiment, a voltage reference circuit is configured to use two differentially coupled transistors to form a delta Vbe for the voltage reference circuit.