Abstract: A circuit for controlled discharge of energy stored in an inductive load, comprising an active semiconductor device (T) connected serially with the inductive load (L) between first and second terminals of a voltage supply source and having a control terminal for connection to a driver circuit (C), and a control circuit (R1, R2, COMP) connected between the inductive load and said control terminal. The control circuit comprises a voltage divider (R1, R2) connected between the inductive load (L) and the first terminal of the voltage supply source, and a comparator (COMP) having first and second input terminals respectively connected to the voltage divider and to a voltage reference and an output terminal which is coupled to the control terminal of the active element (T).

Abstract: The invention relates to a transconductor circuit with a double input and a single output, comprising two input transistors (M1, M2) whose primary conduction terminals (D1, S1, D2, S2) are respectively connected together; in this way, variations in load current and voltage can be made lower, thereby also lowering distortion from changes in their transconductance.

Abstract: A chip card system provided with an offset portable electronic circuit includes a module that integrates one or more electronic components, a reader 4 of this module, an intermediate means 3 directly linked with the reader 4 and a conveyance means 2 to provide for the transmission of information between the module 1 and the intermediate means 3, and vice versa. The intermediate means is a chip card that enables access to standard readers. The module can be used to set up a complex application without any problem as regards available surface areas. Moreover, the reliability obtained is that of the mounting of electronic components. It is far greater than that obtained in the technology of mounting a chip in a chip card.

Abstract: A vertical switched-emitter device structure in which the body of a vertical-current-flow MOS device is formed in a P-type surface epi region, and dielectric isolation laterally separates the body from the surface contact to the buried P-type base region.

Abstract: A phase-locked loop (or frequency-locked loop) based circuit for controlling the drive applied to a DC polyphase motor is disclosed. The disclosed circuit includes a clamp circuit, connected to the input of the motor drive amplifier, for limiting the current applied to the drive amplifier, in order to ensure that the power supply is not overloaded. According to one embodiment of the invention, the clamp circuit includes a buffer amplifier having a source leg and a sink leg. During a current control mode, both the source leg and sink leg of the buffer amplifier are enabled to drive the input of the motor drive amplifier; the buffer amplifier is a differential amplifier and applies a feedback signal from the drive amplifier input to control the current applied thereto according to an input limit signal.

Abstract: A survival sequence register for a read channel employing a variable threshold peak qualification technique, has a first data shift register receiving a logic sum stream of two serial streams of coded digital data, corresponding to qualified peaks detected by a reading pick-up of positive and negative sign, respectively, and a pointer register. A control circuit generates an erase signal when an incoming pulse is recognized as corresponding to a detected peak of the same sign of the previously detected peak. The erase signal is input to logic gates which each drive a reset terminal of a flip-flop of the data shift register, with the exception of the first flip-flop of the register. The pointer register being reset when the control circuit receives a pulse corresponding to a peak of opposite polarity of the detected peak relative to the preceding pulse.

Abstract: A precision resistor, on a semiconductor substrate, formed by using two polysilicon stripes to mask the oxide etch (and ion implantation) which forms a third conductive stripe in a moat (active) area of the substrate. The sheet resistance R.sub.p and a patterned width W.sub.p of the polysilicon stripes and the patterned width W.sub.M and sheet resistance R.sub.M, are related as R.sub.p W.sub.p =2R.sub.M W.sub.M. By connecting the three stripes in parallel, a net resistance value is achieved which is independent of linewidth variation.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: An electronic circuit for controlling an analog quartz clock, particularly for installation in automobiles, has first and second counters for generating control pulses at different rates according to whether the clock is to be operated in a normal mode, or a time-setting mode. In addition, a single 11-bit counter allows "fast" or "slow" resetting of the time by a single push button.

Abstract: A source/sink current generating circuit is arranged to generate source and sink currents which are matched and insensitive to fan out. This is achieved by using a biasing transistor (Q13) between first and second current mirrors which generate respectively the source and sink currents.

Abstract: The disclosure relates to integrated circuits and, notably, to memories. A description is given of a bistable type of programmable, non-volatile memory, namely a memory that can take one state or another by the programming of one of two floating-gate transistors of the cell. To program a cell such as this, there are two transistors for the application of a programming voltage (VPRG). In order that the signals going through the programming paths (in particular the address signals) may not disturb the state of the cell in reading mode, provision is made for two isolation transistors interposed between the transistors for the application of the programming voltage and the drains of the floating-gate transistors. These isolation transistors are made conductive by a signal CAMSEL solely for a programming operation and solely for only one group of cells to be programmed. These cells can be applied notably to the storage of defective address elements in the redundancy circuits of large-capacity memories.

Abstract: A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions have to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.

Abstract: A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.

Abstract: A switching power supply in which the oscillation frequency is dynamically controlled to have an instantaneous frequency value which is reduced when the power line waveform is near its peaks. This is preferably accomplished by a divider circuit, which provides an output current proportional to the ratio between the instantaneous value of the rectified voltage and the long-term-averaged value of that voltage. This output current is fed into a ramp generator, to dynamically shift the frequency of the ramp generator as the output current changes. This circuit is indifferent to power line voltage and frequency (over a fairly wide range), and therefore may be used in different countries having different power standards.

Abstract: A high voltage semiconductor component having a low stray current comprises a central region (N.sup.-) surrounded by P-type layers (P.sub.1, P.sub.2) forming with the central region first and second junctions (J.sub.1, J.sub.2). The first and second junctions have an apparent perimeter on a same main surface of the component. A groove is formed between said apparent perimeters and is filled with a passivation glass (18). The surface of the glass is covered, above the perimeter of each junction, with a metallization (21, 22) contacting the layer of the second conductivity type corresponding to the junction.

Abstract: A driver circuit, for an electronic switch which is to be operated from a clock signal, comprises an inverter driven by the clock signal, and a voltage doubler which is connected to supply the inverter and connected to be driven by the complementary clock signal.

Abstract: In a device for the protection of integrated circuits against electrostatic discharges, the protection structure comprises a thyristor with an N+ region connected to the ground, a P- substrate, a deep N- well forming a gate region, and a P+ region connected to an external connection pad to be protected. The gate region is connected by a low-value resistor (with a maximum value of a few ohms) to the pad. This resistor increases the current for which the thyristor gets triggered and eliminates certain risks of the destruction of the circuit.

Abstract: A data-array processing system with a memory for storing an array of data-elements, a processor to perform a series of operations on data elements stored in a first section (832) of the memory and to copy data from the first section to a second section (830) of the memory after each series of operations, and output hardware, such a video processor and monitor, for outputting the data-elements in the second section. In order to reduce unnecessary copying of data-elements from the first section to the second section, the processor sets flags indicative of each of the of portions (e.g. P, Q, R, S) of the first section which is modified during that processing operation, and checks the flags during the subsequent copying operation to copy only the flagged portions.

Abstract: An innovative circuit for driving the write head. All of the driving transistors are NPN, and are prevented from saturation. This is achieved by shifting and scaling down the differential drive applied to the pull-up transistors, to drive the pull-down transistors with levels such that the pull-down transistors cannot reach saturation. This provides a very simple circuit in which all four of the drive transistors are NPN, and all are kept out of saturation. Moreover, the peak write current applied to the head is precisely limited.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.