Patents Represented by Attorney, Agent or Law Firm Robert Groover
  • Circuit for filtering a signal and integrated circuit comprising such a circuit
    Patent number: 5467053
    Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: November 14, 1995
    Assignee: SGS-Thomson Microelectronics, SA
    Inventors: Sylvie Wuidart, Tien-Dung Do
  • Monolithic integrated bridge transistor circuit and corresponding manufacturing process
    Patent number: 5464993
    Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: November 7, 1995
    Assignee: Consorzio per la Ricerca sulla Microelectronica nel Mezzogiorno
    Inventors: Raffaele Zambrano, Sergio Palara
  • Structure and method for connecting leads from multiple chips
    Patent number: 5461544
    Abstract: A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: October 24, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Charles R. Ewers
  • Graphics rendering systems
    Patent number: 5459835
    Abstract: In a 2-D graphics rendering system having a plurality of processors (PROC 0 to PROC 3) which receive instructions from a common instruction register (IR) and render polygons in a framestore (FS), in order to permit asynchronous performance of the instructions and yet ensure that overlapping polygons are properly rendered, each instruction includes an ordering code, and before writing a pixel to the framestore (FS) each processor checks that the ordering code of the polygon it is rendering is more significant than an ordering code for that pixel stored in an ordering buffer in which case the pixel is written to the framestore (FS) and the order buffer (OB) is updated, but if not the pixel is not written.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: October 17, 1995
    Assignee: 3D Labs Ltd.
    Inventor: Neil F. Trevett
  • Method and architecture for accelerated programming of uniform data into an electrically programmable memory
    Patent number: 5457651
    Abstract: A method for the programming of a data element in an electrically programmable memory in integrated circuit form comprising a data input/output bus, an address bus, a register for the control of instruction sequencing modes and an enable signal (/OE), said signal enabling the data output bus in an active state. When the control register receives a uniform programming instruction, it sends a uniform programming sequencing mode signal so that an inactive state of the enable signal triggers the programming of the data element at a memory address present in the address bus and so that the active state of the enable signal triggers the stopping of the programming operation. Also disclosed is an electrically programmable memory in integrated circuit form, implementing a method such as this. The disclosure can be applied to electrically programmable memories.
    Type: Grant
    Filed: January 3, 1994
    Date of Patent: October 10, 1995
    Assignee: SGS Thomson Microelectronics, S.A.
    Inventor: Olivier Rouy
  • Linear transconductors
    Patent number: 5451859
    Abstract: An integrated transconductor circuit in which the input transistor(s) passes a current across a reference resistor. This conventional arrangement produces current error terms of Vbe/R and Ib. According to the present invention, these terms are compensated by providing a compensation resistor which is matched to the first resistor, and a compensation transistor which is matched to the input transistor, interconnected to feed the appropriate current components to the output. For even better compensation, an additional transistor is optionally added to remove the effect of base current of the compensation transistor. In differential embodiments, the compensation resistor may be bridged or split. Zero, one, or more stages of current mirroring can optionally be used to provide the desired output.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: September 19, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Marc Ryat
  • Method for manufacturing plastic-encapsulated semiconductor devices with exposed metal heat sink
    Patent number: 5445995
    Abstract: A mold is disclosed for semiconductor devices intended for surface mounting, being of a type which comprises a metal plate and a body of solidified plastic resin. It consists of two plates which delimit at least one hollow adapted to receive the plate and to contain resin for forming the device body. Two elements of the mold push the plate from opposed sides against the bottom of the hollow. The hollow has two side extensions which are delimited by the side surfaces of the plate edges, thereby solidified projections are formed thereon which separate readily after the molding process. Thus, a structure is obtained wherein the plate has its bottom surface and two side edge portions fully exposed to allow optimum and controllable soldering to a printed circuit board.
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: August 29, 1995
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Paolo Casati, Pierangelo Magni
  • Stylus operable computer with wireless keyboard in storage bay
    Patent number: 5440502
    Abstract: A pen-operable computer which also functions as a fully keyboard-operable computer. The keyboard contains an independent power supply, and is linked to the main chassis only by an infrared interface. The system chassis is very compact, but includes a full-width docking bay into which the keyboard can be latched for storage. When keyboard interface is desired, the user takes the keyboard module out of its docking bay and uses it in whatever position is most comfortable. When keyboard interface is not desired, the user simply snaps the keyboard module back into its docking bay for safe storage and/or transport.
    Type: Grant
    Filed: December 26, 1991
    Date of Patent: August 8, 1995
    Assignee: Dell USA, L.P.
    Inventor: David S. Register
  • Integrated circuit entirely protected against ultraviolet rays
    Patent number: 5440510
    Abstract: An integrated circuit unerasable memory cell which includes at least one memory cell consisting of a floating gate transistor with drain, source, and gate terminals, and a metallic shield embedded in the semiconductor substrate and covering the cell. Also provided are a diffused region defining a closed loop path on the substrate surface all around the transistor, and having said shield connected peripherally thereto in an unbroken fashion, and first and second wells extending in the substrate from the transistor to outside the diffused region, the first of said wells being connected directly to the gate terminal of the transistor. A contact inside the shield connects the shield's top surface to the cell's source. A protection diode (inside the shield) prevents charging of the floating gate during manufacture.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: August 8, 1995
    Assignee: SGS-Thomson Microelectronics, S.R.L.
    Inventors: Paolo Caprara, Emilio Camerlenghi
  • Self-aligned method for forming contact with zero offset to gate
    Patent number: 5439846
    Abstract: A method for self-aligned zero-margin contacts to active and poly-1, using silicon nitride or other dielectric material with low reflectivity and etch selectivity to oxide for an etch stop layer and also for sidewall spacers on the gate.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: August 8, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Loi Nguyen, Robert L. Hodges
  • Circuit for the detection of a high threshold of a supply voltage
    Patent number: 5440255
    Abstract: A circuit for the detection of a high threshold supply voltage comprising a voltage divider and an inverter. The voltage divider is formed by a reverse-biased voltage breakdown device, such as a Zener diode, and a resistive element, such as a forward-biased transistor or a resistor. The use of the reverse-biased voltage breakdown device in the divider makes the detection threshold voltage (Vo) of the circuit stable and precise even with variations in threshold voltages due to temperature and manufacturing process variations.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: August 8, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Richard Fournel
  • Voltage threshold detection circuit with very low power consumption
    Patent number: 5440263
    Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: August 8, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Richard P. Fournel, Laurent Sourgen
  • Enhanced planarization technique for an integrated circuit
    Patent number: 5435888
    Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: July 25, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Alex Kalnitsky, Yih-Shung Lin
  • Electrically programmable integrated memory with only one transistor
    Patent number: 5436479
    Abstract: A novel electrically programmable and erasable memory cell, comprising a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain and the floating gate. The capacitive coupling between the source and the floating gate is low, as is normally the case. Preferably, the control gate only partly covers the floating gate. Another part of the floating gate is covered by a semiconductor layer connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: July 25, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Jean Devin
  • Electronically configurable connection device
    Patent number: 5434982
    Abstract: The use of electromechanical devices for the configuration of the address for access to a peripheral unit in a data-processing system is avoided by replacing them with a non-volatile EEPROM-type memory. The dam in non-volatile memory is read as soon as the peripheral unit is put into operation, and the information that it delivers is stored in volatile memory and used as a comparison address to validate the operation of the peripheral unit.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: July 18, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Philippe Calzi
  • Resistor-capacitor-transistor type integrated circuit, method for the manufacture of such a circuit and application to an oscillator
    Patent number: 5430319
    Abstract: A resistor-capacitor-transistor type of integrated circuit comprises mainly a non-self-aligned N diffusion bar 1 covered with a polysilicon plate, and a drain type N diffusion, self-aligned by the polysilicon plate. The resulting structure is a distributed resistor-capacitor-transistor quadripole whose main characteristics are that it is very compact and that the time taken by the capacitor to get discharged through the transistor is independent of the dimensions of the structure.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: July 4, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Richard P. Fournel, Francois Tailliet
  • VDMOS transistor with improved breakdown characteristics
    Patent number: 5430316
    Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: July 4, 1995
    Assignee: SGS-Thomson Microeletronics, S.r.l.
    Inventors: Claudio Contiero, Paola Galbiati, Lucia Zullino
  • Computer system with clock shared between processors executing separate instruction streams
    Patent number: 5428754
    Abstract: A multiprocessor system which includes a control processor and a high-level data-transfer processor. Both of these two processors are docked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle time on that particular cycle. Thus, the control processor 110 and the data transfer processor 120 are enabled to run synchronously, even though they are concurrently running separate streams of instructions.
    Type: Grant
    Filed: March 21, 1989
    Date of Patent: June 27, 1995
    Assignee: 3DLabs Ltd
    Inventor: David R. Baldwin
  • Stress test for memory arrays in integrated circuits
    Patent number: 5424988
    Abstract: A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: June 13, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: David C. McClure, James Brady
  • Low capacitance protection circuit for telephone equipment
    Patent number: 5422777
    Abstract: An overvoltage protection circuit comprises three protection components (21, 22, 23) connected by their first terminal to a common point (C) and by their second terminal to a first conductor (A), second conductor (B) and ground, respectively. Each protection component comprises the anti-parallel association of a protection component (T1, T2, T3) and a diode (D1, D2, D3), the common point being connected to a same polarity terminal of each protection component. In case one of the conductors exhibits, at the normal state, a polarization difference higher than the other with respect to ground, the cathodes or anodes of the protection components are connected to the common point according as the higher polarized conductor is negative or positive with respect to ground.
    Type: Grant
    Filed: August 23, 1993
    Date of Patent: June 6, 1995
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Robert Pezzani