Abstract: The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.

Abstract: A precision resistor, on a semiconductor substrate, formed by using two polysilicon stripes to mask the oxide etch (and ion implantation) which forms a third conductive stripe in a moat (active) area of the substrate. The sheet resistance R.sub.p and a patterned width W.sub.p of the polysilicon stripes and the patterned width W.sub.M and sheet resistance R.sub.M, are related as R.sub.p W.sub.p =2R.sub.M W.sub.M. By connecting the three stripes in parallel, a net resistance value is achieved which is independent of linewidth variation.

Abstract: A method for sorting the k greatest ones of a sequence of n incoming data values, by: a) sequentially writing each data value into one of n one-word memories, in a word format which includes, in decreasing weight order, the following bits: a first inhibition bit (MI), a second selection bit (MS), third data bits (MD), and fourth bits (MP) representative of the position of the incoming datum; b) setting the first bits (MI) of the n words during the arrival of the first signal; c) while writing each data value, resetting the first (MI) and second (MS) bits of the corresponding word; and d) between the arrivals of the (n-k).sup.th datum and n.sup.th datum, detecting the smallest word stored in the memories and setting its second bit (MS).

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage during a system's "dead" time. This is done with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial precharging with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

Abstract: A variable gain amplifier which includes a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; and a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.

Abstract: A packaging structure is disclosed for a semiconductor device, having a body configured to include at least one part provided with contact terminals and shaped to form a connector member for direct coupling to a standard connector member from an external circuit. A connector assembly is also disclosed which is fully sealed from moisture and comprises the packaging structure.

Abstract: A personal computer which a microcontroller, separate from the main processor, is used for power-management functions. Under certain conditions, this power-management microcontroller can take control of the system bus. This provide BIOS-independent power management, and permits sophisticated power management to be performed without placing any burden or constraints on the user's choice of operating system or application software.

Abstract: An electric blanket system which runs from an AC power input, and does not use a transformer; but the power supply is rectified and regulated, to reduce the AC component of current by 90% or more (preferably 99% or more). The blanket itself uses a field-cancelling resistor layout, to achieve a further reduction of 95% or more (preferably 99% or more). The combination of these techniques provides a reasonably cheap way to bring the low-frequency magnetic field strength down to acceptable levels.

Abstract: A computer system including an input/output (I/O) connector for connecting to an external data peripheral, where the computer includes circuitry for detecting the presence or absence of a load on a first pin and for providing power to the external data peripheral through a second pin of the I/O connector. In this manner, the external data peripheral need not include a separate power supply, but instead is sensed and powered by the computer itself through the I/O connector. In the preferred embodiment, the I/O connector is coupled to parallel port circuitry for interfacing to an external printer, and also to a floppy controller for interfacing with an external floppy drive, where the computer system further includes circuitry to switch from the printer controller to the floppy controller when an external floppy drive is connected to the I/O connector. In this manner, the same I/O port automatically serves either an external printer or an external floppy drive.

Abstract: A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract: A finger-emitter power transistor including a substrate suitable for operating as the collector of the power transistor, an epitaxial layer superimposed over the substrate (and providing a base region for the transistor), and at least one buried emitter region (for each finger of the device) below the surface of the epitaxial layer. Each buried emitter region is provided with at least one connection area to an emitter surface metallization. The connection areas between the emitter regions and their emitter surface metallization are made in various widths to provide a ballast resistance of an adequate value.

Abstract: A photolithographic system wherein optical fiber routing is used to combine two or more ultraviolet light sources for reticle illumination.

Abstract: A high-voltage switching circuit comprising two arms, wherein each arm has a P-channel load transistor, a forward biased diode and an N-channel switching transistor series-connected between the high voltage and the ground. The gate of the N-channel transistor is controlled by a switching signal C in one arm and by the complementary switching signal C in the other arm. Such a structure enables the stress undergone by the load and switching transistors of the switching circuit to be reduced by several magnitudes.

Abstract: An improved circuit for controlling the maximum current in a MOS power transistor, in which resistor is in series with the drain-source path of the MOS power transistor. The supply terminal of a transconductance operational amplifier is connected to the output of a voltage-raising or charge pump circuit which can output a voltage higher than that of the voltage supply to which the drain of the MOS transistor is connected. The inputs of the amplifier are connected to the resistor and its output is connected to the gate of the MOS transistor so that, in operation, the maximum current flowing through the power transistor is limited to a value proportional to a reference voltage.

Abstract: An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.

Abstract: A method for starting-up in a desired forward sense of rotation a multiphase, brushless, sensorless, DC motor, while limiting the extent of a possible backward rotation. First, a predetermined initial phase is excited (thereby accelerating the rotor toward an equilibrium position for that initial phase), for only a fraction of the time necessary for the accelerated rotor to travel through a nearest angular position which would determine a "zero-crossing" in the waveform of any one of the back electromotive forces (BEMFs) which are induced by the rotor on the windings of the motor. After the elapsing of this brief impulse of excitation, the sign of the BEMFs induced in the windings of the motor are digitally read thus producing a first reading.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: An integrated circuit transconductor stage which suppresses the dependence on temperature and production process variables of a differential transconductor stage. A negative feedback relation is used, where the output of the transconductor stage is connected to an additional current generator (which is referenced to a precision external resistor), to a capacitor, and also to the gate of a PMOS transistor which sources current to a polarization stage, which in turn sources current to the transconductor stage, or to multiple transconductor stages.