Abstract: The contrasting requirements of low power consumption during operation and ability to function under drastic drops of the supply voltage at start-up of output power stages of an electric system of self-generation and recharge of a storage battery, are satisfied by an output power driving stage composed of a bipolar transistor and a field effect transistor, functionally connected in parallel to each other and having independent control terminals. A control signal is selectably switched either to the base of the bipolar output transistor or to the gate of the field effect output transistor, depending on the level of the supply voltage. A comparator comparing the voltage present on the supply node with a reference voltage controls a selection switch. The low threshold of the bipolar transistor ensures functioning at start-up, while the field effect transistor provides a low power consumption during normal running conditions.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which essentially utilizes a current generator and a circuit to apply zero volts to the gates of all the cells of the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is the associated detection method and a memory circuit using a detection circuit such as this.

Abstract: A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

Abstract: To acquire measurement data elements during a tomography type experiment in nuclear medecine, with a gamma camera having two detector heads, each of these heads is oriented on a sighting center P while the set of two heads rotates about a center of rotation Ia of the apparatus, the center of rotation being offset from the sighting center. It is shown that this approach provides speedier operation for the acquisition and also contributes to the preparation of tomography images that are more precise and more easily computed.

Abstract: A portable computer system wherein the printer port can be used, at the user's option, not only for connection to a printer, but also for connection to an external floppy disk drive. If the BIOS determines that there is an external floppy drive attached, the BIOS disables the normal operation of the parallel port in order to allow the external floppy to operate.

Abstract: To connect an apparatus to a transmission channel, use is made of a device comprising a first coupling circuit to couple the device to the channel, a second circuit to process the signals received or transmitted and to verify that they conform to a pre-set standard, and a third circuit, normally a microprocessor, connected firstly to the processing circuit and secondly to the apparatus to make it carry out instructions corresponding to the information elements received. The second circuit comprises a control register associated with the type of the signals transmitted and a buffer memory to receive the signals transmitted or to be transmitted. The microprocessor is then made to carry out the instructions loaded into a program memory of this microprocessor as a function of the state of this control register.

Abstract: A circuit for regulating the charging time of the output node of an amplifier at start up. The output node commonly comprises an external soft-start capacitor charged by a current delivered by a pull-up transistor of a push-pull output stage of the amplifier, through a decoupling diode that is functionally connected between the output node of the amplifier and a terminal of the external soft-start capacitor. The present application provides a current mirror feed back circuit capable of mirroring the charge current of the external soft-start capacitor onto the driving node of the pull-up transistor of the output stage of the amplifier. The regulating circuit permits use of an external capacitance of extremely small size. Upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.

Abstract: A power-on reset circuit which employs a supply voltage sensing branch for triggering a first inverter of a pair of cascaded inverters. The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator, which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing branch into a subthreshold operating condition.

Abstract: A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.

Abstract: A method for forming field oxide regions on an integrated circuit device includes the steps of providing doped regions for formation of active devices. After the doped regions have been formed, a thick field oxide layer is grown over the entire surface of the device. Field oxide regions are then defined using masking and anisotropic etching steps which provide approximately vertical sidewalls for the field oxide regions, and which do not result in the formation of bird's beaks. Since the active regions are defined prior to formation of the field oxide regions, the active regions extend under the field oxide regions and do not give rise to edge effects.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.

Abstract: A padded cover for use with a mattress which provides added postural support (as well as extra thermal insulation and padding). The padded cover includes a sheet of support material which covers essentially the full length of the mattress. This sheet of support material is stiffened over the middle part of the mattress length. Thus, this arrangement provides extra firmness under the torso, while maintaining an essentially flat upper surface. This cover structure can be retrofitted to existing mattresses. The disclosed innovations also provide improved methods for manufacturing bedding material with stable and longitudinally nonuniform postural support. For example, in the presently preferred embodiment, three layers are fed into a standard quilting machine: an upper layer of ticking, a middle layer of convoluted-foam support material, and a bottom layer of quilt backing. The support material thus is quilted between the two other layers, giving a quilted fabric that may be made into a mattress cover.

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.

Abstract: A system for storing and processing an array of data-elements formatted as a plurality of pages of the data elements, and especially for use in a demand-paged dual memory system, comprises a memory in which each memory location has a capacity of, for example, 32 bits and a processing means for processing data elements and reading the data elements from and/or writing them to the memory. In order to enable full use to be made of the memory and to facilitate the use of demand-paging when dealing with data-elements having less bits, for example 16 or 8 bits, a plurality of such data-elements are stored at different bit levels in each memory location so that at no memory location is there stored data-elements from more than one page.

Abstract: A protection device, for a telephone (or other load) 27 in series with an external protection transistor 2, includes a sensor 6 for detecting common-mode current into the load. The output of the sensor 6 is connected to affect a current source/sink combination, and imbalance in this source/sink combination produces a voltage shift which is indirectly connected to control the protection transistor.

Abstract: A circuit for providing a reference current comprises first and second matched transistors, each of which has a control node and a controllable path and each of which is connected so that a current setting resistor is in the controllable path of the second matched transistor, the current setting resistor having a value, current set in the controllable path of the second matched transistor is related to a difference in voltage characteristics between the first and second matched transistors and to the value of the current setting resistor, and third and fourth matched transistors, each of the third and fourth matched transistors having a controllable path connected respectively to the controllable paths of the first and second matched transistors, and control electrodes of the third and fourth matched transistors connected together; a set of output transistors connected to the circuit to supply the reference current in dependence on a set current; and a fifth transistor having a controllable path between a bia

Abstract: A package for discrete semiconductor devices, wherein the insulating characteristics of the package are improved by introducing an opening, indentations, grooves and positioning holes in the metal plate and shaping in appropriate form the retractable positioning pins of the metal plate in the molding die.

Abstract: In an integrated circuit with protection against electrostatic discharges, there is provided a first voltage limiter connected between a pad to be protected and a ground bus. This first limiter is placed the peripheral part of the integrated circuit in the vicinity of the pad And there is provided a second voltage limiter directly connected to a circuit element to be protected. This second limiter is placed in the useful part of the integrated circuit and not in the peripheral part. Thus, the risks related to the resistors of the ground bus, crossed by high electrostatic discharge currents, are avoided.

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.

Abstract: A voltage-current amplification circuit comprises two sub-circuits (B1, B2), each of which comprises a differential amplifier (D), a resistor (R4), a transistor (T), and a first switch (K1) connected between the transistor base and ground. Each sub-circuit (B1, B2) also comprises an additional amplifier (A1, A2), and an additional resistor (R2a, R2b), respectively. The inputs of the additional amplifiers being connected to ground through a common resistor (R) and to the emitters of the two transistors through a common resistor (R1). Each sub-circuit further comprises a second switch (K2) formed by a single transistor.