Abstract: A voltage converter including a transformer having a primary winding connected in series with a switch for cutting-up a supply voltage and having a secondary winding associated with a capacitor providing a D.C. low voltage, and a self-oscillating control circuit of the switch for detecting the end of the demagnetization of an auxiliary winding of the transformer, to turn the switch on, and for detecting the current in the on-state switch to turn it off when this current reaches a reference point. The reference point is made variable according to the voltage across the auxiliary winding.

Abstract: A photodetector including an amorphous silicon photodiode having its anode connected to a reference voltage, an initialization MOS transistor connected between the cathode of the photodiode and a first supply voltage to set the cathode to the first supply voltage during an initialization phase, and means for measuring the voltage of the photodiode cathode, including saturation means for bringing the photodiode cathode to a saturation voltage close to the reference voltage immediately before the initialization phase.

Abstract: This method and apparatus described herein imposes masking factors to the determined quantization step sizes of macroblocks of a video sequence such that encoding efficiency is increased. A conditional masking method can be used to take advantage of the fact that P-pictures are more important than B-pictures in terms of motion and scene updates as coding noise in such updates are likely propagated by P-pictures. The masking can be applied conditionally to motion/scene update regions of a picture such that coding noise is reduced and therefore bits are saved from less propagation of this noise. Before encoding each macroblock of a picture from an input video sequence, a video encoder with conditional masking determines if the macroblock type belongs to a significant motion or scene update region. A conditional masking factor is then determined for the macroblock based on the determined macroblock type and the picture coding type.

Abstract: A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.

Abstract: A charge pump for negative voltages, having at least one stage including a high-voltage terminal and a low-voltage terminal; a first branch and a second branch, which are symmetrical and are connected between the high-voltage terminal and the low-voltage terminal and each of which comprises a respective first transistor and a respective second transistor. The first and the second transistors are all triple-well MOS transistors of one and the same polarity type.

Abstract: An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

Abstract: According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; if it is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

Abstract: The present invention relates to method to improve RF measurements accuracy on an automatic testing equipment (ATE) for IC wafers by implementing a test board de-embedding phase, wherein each wafer includes a device under test located on a wafer die plane and being contacted by probecard needles of a probecard that is coupled to a configuration board through a probe interface board (PIB), the method including the following phases: performing an automatic calibration phase of the testing equipment up to an internal plane located inside the automatic testing equipment; performing a calibration plane transfer up to a plane of the configuration board using a predetermined number of calibration standard loads realized on the wafer; performing a test boards de-embedding phase up to the wafer die plane.

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: The present invention provides a thermal sensor circuit for sensing the temperature of an integrated circuit chip, the thermal sensor circuit including: an output comparator for comparing a reference voltage, Vref, with a sensed voltage, Vsense, the sensed voltage being measured over a sensing resistor relative to the ground potential of the circuit; a first circuit to which a reference voltage line in connected to measure Vref; a first current mirror providing a first current input to the first circuit and to a compensation circuit; and second current mirror providing a second current input to the compensation circuit and to the sensing resistor.

Abstract: An integrated cache memory circuit is provided comprising a tag RAM, a comparator and a data RAM. Each of the tag RAM and the date RAM have an array of memory cells and plural sense amplifiers. Each memory cell of the RAMs is connected via a respective bit line to one of the plural sense amplifiers. The sense amplifiers of the tag RAM have respective outputs coupled to a first input of the comparator. The comparator having a second input for address information and an output for selectively enabling data output from sense amplifiers of the data RAM. The memory cells of the tag RAM are arranged to have a higher current drive than the memory cells of the data RAM.

Abstract: The method of a protection circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element is connected to the input of the circuit, downstream of the switch. The switch is temporarily opened by a control signal generated by a monostable circuit when detecting switching of power elements belonging to an electronic device embedding the protection circuit. When the switch is open, the memory element supplies the circuit with the reference voltage previously stored. In this way, switching of the power element that might cause noise on the reference voltage cannot disturb the circuit and thereby cannot cause a faulty operation of the latter.

Abstract: A microactuator comprises a motor element including a stator and a rotor capacitively coupled to the stator; an actuator element having a circular structure; and a transmission structure interposed between the motor element and the actuator element to transmit a rotary movement of the motor element into a corresponding rotary movement of the actuator element. In particular, the transmission structure comprises a pair of transmission arms identical to each other, arranged symmetrically with respect to a symmetry axis of the microactuator. The transmission arms extend between two approximately diametrically opposed regions of the rotor to diametrically opposed regions of the actuator element.

Abstract: A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract: An optical device is formed by a first chip and a second chip bonded together. The first chip (4 has an optical layer of glass housing an optical circuit; the second chip has a body of semiconductor material housing integrated electronic components and coated with a bonding layer of glass fixed directly and contiguous to the optical layer of the first chip. The bonding layer delimits cavities facing corresponding cavities in the first chip in positions corresponding to the intersection points of waveguides constituting the optical circuit. The cavities are filled with a liquid having the same refractive index as the waveguides. Underneath each cavity, in the body of semiconductor material there is present a resistor, which, when traversed by current, causes formation of a bubble inside the chamber and deflection of the light beam traversing a waveguide towards a different waveguide.

Abstract: A method for generating a fault signal in a system voltage regulator by a phase signal includes detecting the system voltage and phase signal; comparing the system voltage and phase signal with respective fault levels; and generating a fault signal upon either the system voltage or the phase signal falling below the respective fault level of the fault levels. The fault signal generating method also inhibits generating a fault signal using a drive signal of the system voltage regulator. A diagnostic circuit for a system voltage regulator is also disclosed.

Abstract: The voice message managing method for a voice data recording/playing/editing electronic device, said electronic device including a memory device having a first memory area and a second memory area, includes the steps of memorizing, in the first memory area, a plurality of voice messages, and of memorizing, in the second memory area, information regarding the plurality of voice messages. The method also includes the steps of organizing the first memory area as a sequence of blocks, and of memorizing in each block a portion of voice message. The method moreover comprises the steps of defining a list (FBL) containing information on the status of the blocks and memorizing the list in a first memory sub-area of the second memory area, and of defining a table containing a plurality of first vectors associated to respective voice messages and memorizing this table in a second memory sub-area of the second memory area.

Abstract: A voltage regulator having an output terminal adapted to being connected to a load, including a device for limiting the current flowing through the load to a first threshold current if the voltage of the output terminal is lower than a threshold voltage, and to a second current threshold higher than the first current threshold if the voltage of the output terminal is greater than the threshold voltage.

Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.