Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

Abstract: A selective silicidation process for electronic devices that are integrated on a semiconductor substrate is presented. The devices have a number of active elements formed with gate region that has at least one polysilicon layer. The process begins with depositing a dielectric layer over the entire surface of the semiconductor. Then portions of the dielectric layer are removed to expose the polysilicon layer in the gate regions. Next, a layer of a transition metal is deposited and subjected to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer over the gate regions.

Abstract: A method for manufacturing a thick oxide layer on a semiconductive substrate is presented. The method comprises the formation of at least one layer of dielectric material on said substrate, followed by formation of a plurality of trench regions of a predetermined width in the substrate. A plurality of corresponding walls of semiconductive material of a second predetermined width are delimited. Finally, the semiconductor is submitted to a thermal treatment to oxidize said walls.

Abstract: A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: An electrical connection structure having connection elements which electrically connect a movable part to a fixed part of a microelectromechanical device, for example a microactuator. The movable part and fixed part are separated by trenches and are mechanically connected by spring elements, which determine, together with the connection elements, the torsional rigidity of the microelectromechanical device. Each connection element is formed by multiple sub-arms connected in parallel and having a common movable anchorage region anchored to the movable part, and a common fixed anchorage region anchored to the fixed part, whereby the mechanical resistance of the connection elements is negligible. The sub-arms have a width equal to a sub-multiple of the width necessary in case of a single connection element for the latter to have a preset electrical resistance, which is determined in the design.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

Abstract: An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

Abstract: Interface circuitry is disclosed for interfacing between an operational circuit, a microprocessor, for example, and data storage circuitry, for example direct Rambus memory. The interface circuitry comprises buffer circuitry coupled between the operational circuitry and the data storage circuitry which is arranged to store data access requests received from the operational circuitry and to store data retrieved from the data storage circuitry. The buffer circuitry comprises an output for supplying the data access request signals to the data storage circuitry and to supply the stored data from the data storage circuitry to the operational circuitry. In use, the number of stored data access request signals decreases as the amount of stored data from the data storage circuitry increases. Similarly, the number of stored data access request signals increases as the amount of stored data from the data storage circuitry decreases.

Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal s

Abstract: Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

Abstract: A method and apparatus for subband phase flag determination for coupling of channels in a dual channel audio encoder is based on a psychoacoustic model of the human auditory system. The method and apparatus are applicable to audio encoders which utilize a coupling channel to combine certain frequency components of the input audio signals. The method ensures a least square error between the original channel frequency coefficients at the encoder and the estimated coefficients at the decoder by determining the sign of the dot product of the coefficients for one of the channels and the coupling coefficients. No restriction is placed on the strategy utilized for generating the coupling channel coefficients or the coupling coordinates.

Abstract: Method for manufacturing an SOI wafer. On a monocrystalline silicon wafer, forming protective regions having the shape of an overturned U, made of an oxidation resistant material, the protective regions covering first wafer portions. Forming deep trenches in the wafer which extend between, and laterally delimit the first wafer portions, completely oxidizing the first wafer portions except their upper areas which are covered by the protective regions, to form at least one continuous region of covered oxide overlaid by the non-oxidized upper portions. Removing the protective regions, and epitaxially growing a crystalline semiconductor material layer from the non-oxidized upper portions.

Abstract: A method for correction of errors in a word stored in multi-bit memory cells includes associating a full error code, which includes bit error codes and a set error code, for each set of bits of the word stored in a single memory cell. The method includes associating, with each single error, a bit error code which is not associated with other errors and which is indicative of a position of the bit in the word. The set error code is computed based on the bit error codes associated with the bits in the set. The method also checks to make sure that the full error code for the set has not already been associated with other errors. If the error code has already been used for another error, then the method changes both the set error code and at least one of the bit error codes.

Abstract: A switched capacitor circuit comprising an operational amplifier, having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential. The operational amplifier is provided with a negative feedback network including a first capacitive element which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element which has a first terminal alternately connected to the second input terminal of the operational amplifier and to a reference potential, and a second terminal connected to a first circuit node which is alternately connected to a signal input terminal and said first output terminal of the operational amplifier. The circuit further includes a third capacitive element connected between the circuit node and a reference potential.

Abstract: Presented is an EEPROM circuit comprising: a program array of a matrix of EEPROM cells arranged in columns and rows, a data array of a matrix of EEPROM cells arranged in columns and rows, the cells of the program and data array capable of being written, read, and erased; a reference voltage circuit coupled to the program array capable of producing voltages used to write to and erase data from the program array; a current generation circuit coupled to the program array for supplying current to the program array in operation. Advantageously according to the invention, the reference voltage circuit and the current generation circuit are additionally coupled to the data array. Moreover, the EEPROM circuit further comprises means for selectively connecting at least one of the rows of the program array to one of the rows of the data array, and for selectively connecting at least one of the columns of the program array to one of the columns of the data array.

Abstract: A drive circuit for controlled edge power elements is described. In one embodiment the drive circuit for controlled edge power elements comprises: a first integrating circuit having a first input suitable for receiving in input a first drive signal; an integrating capacitor coupled to said integrating circuit; a first power element driven by said first integrating circuit and suitable for driving a load, said load having a first terminal. The said first integrating circuit includes a first current amplifier and said integrating capacitor is coupled between said first input and a predetermined reference voltage.

Abstract: It is described a circuit generating a stable reference voltage with respect to temperature, which circuit is connected between first and second voltage references and comprises at least one current generating circuit adapted to inject a reference current into a resistive element connected between a base terminal of a bipolar transistor and an additional voltage reference. The bipolar transistor is connected between the first and second voltage references and to an output terminal of the generator circuit whereat the stable reference voltage with respect to temperature is. The generator circuit further comprises at least another resistive element, feedback connected between the output terminal of the generator circuit and the base terminal of the bipolar transistor to enable injecting additional current, having reverse dependence on temperature from the reference current, into the resistive element.

Abstract: A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.