Abstract: A bus interface having a first circuit based on a first pair of transistors of opposite types having a control electrode and a common electrode for providing a first output potential. A second circuit has a second pair of transistors of opposite types and having a common electrode for providing a second potential switching in opposite direction from the former. This device has a first capacitive coupling means for feeding a portion of the signal existing at said first potential back into said control electrode of said second transistor pair and second capacitive coupling means for feeding a portion of the signal existing at said second potential back into said control electrodes of said first transistor pair. Thus variations between the rise and decay times of the transistors of each pair can be compensated for.

Abstract: A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.

Abstract: The invention concerns an intgrated inductor (20), consisting of a flat winding of one or several turns (21, 22, 23) made of a conductive material above a substrate provided with at least a subjacent conductive level wherein is produced, through a contact pick-up strip (12′), at least an intersection of the winding, the width of at least one turn and/or one interval between two turns being reduced in line with said contact pick-up strip.

Abstract: A regulated voltage-boosting device provides a charge-pump circuit, which has an input terminal receiving a first voltage and an output terminal supplying a second voltage higher than the first voltage. The regulated voltage-boosting device provides a plurality of voltage-boosting stages that can be selectively activated and deactivated. The regulated voltage-boosting device provides an automatic-selection circuit for activating a number of voltage-boosting stages which is correlated to the first voltage and to the second voltage.

Abstract: An input digital signal is encoded by subjecting it to a first convolutional coding step followed by an interleaving step and a second convolutional coding step. The serial concatenated convolutional coded signal thus obtained is then subjected to modulation by means of a two-dimensional modulation scheme such as M-PSK or M-QAM. The corresponding decoding process involves an iterative decoding algorithm based on cascaded logarithmic soft-input soft-output processing steps.

Abstract: A driving circuit for piezoelectric actuators comprises a chip of semiconductor material integrating both an interface circuit receiving at input a control signal generated by a control logic unit, and a power circuit driving the piezoelectric actuators. The power circuit is directly connected to the output of the interface circuit.

Abstract: A method for encoding frequency coefficients in an AC-3 Encoder. The method includes: representing frequency coefficients in theform of a respective exponent and mantissa; coding the exponents; and shifting the mantissas to compensate for changes in the exponent values, wherein the exponents comprise an original exponent set (e0, e1, . . . en−1) which is mapped to a new exponent set (e0′, e1′, . . . , e′n−1) after coding, so as to satisfy: ∥e′i+1−e′i∥<D, where i=0, . . . , n−1 and D is a maximum allowed difference between two consecutive exponents, and e′i≦ei.

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract: Binary words are converted between a non-encoded format and a compressed encoded format, in which the binary words are, at least in part, represented by encoded bit sequences that are shorter than the respective binary word in the non-encoded format. The shortest encoded bit sequences are selected according to the statistical recurrence of the respective words in the non-encoded format, and associated with the binary words with higher recurrence are encoded bit sequences comprising bit numbers that are accordingly smaller. The correspondence between binary words in non-encoded format and the encoded bit sequences associated to them is established by means of indices of an encoding vocabulary. The conversion process includes: arranging the indices in an ordered sequence; organizing the sequence into groups of vectors; splitting each group into a given number of vectors; and encoding the vectors independently from one another.

Abstract: A test handler apparatus, having a treatment area; a testing station in the treatment area; and an output unit connected to an output of the treatment area. An input unit picks singulated or stripped packages and unloads them on carrier boats in a loading zone; a conveyor mechanism transfers the carrier boats from the loading zone through the treatment area to the testing station and from the testing station to the output unit. In practice, the carrier boat forms a universal carrier which is able to contain multiple singulated or strip packages for the purpose of testing. Placing packages onto carriers with standardized dimension allows handler equipment to accommodate the packages in singulated or strip condition.

Abstract: A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

Abstract: A memory device having an associative memory for the storage of data belonging to a plurality of classes. The associative memory has a plurality of memory locations aligned along rows and columns for the storage of data along the rows. Each memory row has a plurality of groups of memory locations, each storing a respective datum, wherein groups of memory locations adjacent along one and the same row store data belonging to different classes. Groups of memory locations adjacent in the direction of the columns and disposed on different rows store data belonging to one and the same class. Each class has data having a different maximum lengths. The device is particularly suitable for the storage of words belonging to a dictionary for automatic recognition of words in a written text.

Abstract: A digital image processing circuit for replacing an input code associated with a pixel of the image with an output code selected in a first memory containing a set of codes, including an input bus for receiving the input code, an output bus for providing the output code, said first memory, means of address calculation of the first memory, means of address selection of the first memory between the input code and an address code generated by the address calculation means, a second memory for containing an address code generated by the address calculation means, and means of selection of the output code between a code read from the first memory and said code contained in the second memory.

Abstract: A wave-shaper device having an output terminal for providing a first periodic analog signal with a first frequency, the wave-shaper device including an oscillator having an output terminal for providing a second periodic analog signal with a second frequency which is multiple with an even factor of the first frequency, and means for obtaining the first analog signal from the second analog signal.

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any deviations in the current from a nominal value. In particular, a reference current is supplied to a reference cell by means of a second capacitive element; next, a first voltage present on the second capacitive element is measured; finally, the memory cell is deactivated when the first voltage is equal to a second voltage, which is constant.