Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: A cache memory and method for operating a cache memory are provided which comprise a tag RAM, tag RAM sense amplifier circuitry, data RAM sense amplifier circuitry and decision circuitry. Timing difficulties exist in determining whether or not a hit has occurred and in outputting the data from the data RAM upon occurrence of a hit. Upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and is compared with input address information. A decision is reached as to whether or not identity exists. Only when the result of that decision has been validly determined can data be output.

Abstract: The present invention relates to a process for removing post-etch residues or polymers from the surface of semiconductor devices which comprises treating the semiconductor device with an aqueous ammonia or ammonium hydroxide solution, optionally containing ozone for a time sufficient to effectively remove said post-etch residues or polymers from the surface of the semiconductor device and rinsing the semiconductor device with ozonized water, i.e. water enriched with ozone, in which water is preferably deionized (ozone-DIW).

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: An interconnect system includes an arbitration unit for arbitration among a plurality of sources or initiators requesting access to resources or targets. The arbitration unit selectively grants the initiators access to the targets as a function of respective priorities. The system includes a programmable control unit for programmably choosing the priorities in question out of group of at least two different priority schemes including a positional fixed priority, programmed fixed priority, and a variable priority based on a respective threshold latency values associated to the initiators.

Abstract: A pull-up circuit for input/output terminals of electronic appliances is disclosed. The circuit is arranged between an input/output terminal and a supply voltage terminal and includes a first transistor and a resistance serially connected and coupled between the input/output terminal and the supply-voltage terminal and circuitry suitable for driving the transistor so as to switch it on or off depending on whether the values achieved by the voltage of the input/output terminal belong or do not belong to a set range of voltage values within the supply-voltage value.

Abstract: A system for controlling the speed of an arm of a disk drive, including a feedback circuit for generating a feedback signal representative of the speed of the arm, and a drive circuit for comparing the feedback signal with a predetermined command signal representing a command speed, and adjusting a drive signal for a motor to drive the arm at the command speed. The feedback signal, which represents the back EMF of the motor, is compared with the command signal to determine an acceleration state of the arm and the acceleration state is used with a previous acceleration state to determine whether to adjust a predetermined level at which the motor is driven.

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region with the opposite conductivity from the first. The device also includes an interface structure between the two regions, of substantial thickness and limited planar size, that includes a trench filled with dielectric material. A method of manufacturing the electronic power device includes forming a silicon oxide-filled trench. The method includes forming, in the substrate, a plurality of small trenches having predetermined widths and -being delimited by a corresponding plurality of semiconductor material walls having second predetermined widths.

Abstract: A current source using a bandgap voltage circuit includes a current gain circuit between the output of the bandgap circuit and the current output transistor. On-off control is provided by a switchable bias circuit providing an ON potential to start the bandgap and a clamping circuit opening the feedback loop.

Abstract: A circuit includes a microprocessor, an MPEG decoder for decoding an image sequence, and a memory common to the microprocessor and to the decoder. The circuit also includes a circuit for evaluating a decoder delay, a control circuit for, if the decoder delay is greater than a predetermined level, granting the decoder a memory access priority, and otherwise, granting the microprocessor the memory access priority.

Abstract: The invention relates to a monolithically integrated telephone circuit for driving wide-band telephone lines and transmitting digital data at a very high frequency. The telephone circuit is powered from a battery DC supply providing a pair of voltage references. The telephone circuit includes an output circuit portion including a pair of differential output stages, each having a pair of inputs and being connected with its output to a respective lead of a two-wire telephone line. The telephone circuit also includes a device for deriving a reference voltage from the supply voltage, and includes a low-voltage supply network which is input a DC signal and produces a voltage reference to be added to the reference voltage for delivery to one input of each output stage. The other input of each stage receives an AC signal in order to present at the circuit output a suitable AC+DC differential voltage for driving the telephone line.

Abstract: The invention provides a method for removing noise spikes from an electrical input signal having an AC component, comprising the steps of determining the actual rms value of the input signal, low pass filtering the input signal, producing a variable offset, said variable offset being a function of the actual rms value, forming a variable threshold by superimposing the variable offset to the low pass filtered signal, comparing the input signal to the variable threshold, creating a spike detection signal when the input signal passes the variable threshold, and blanking the input signal during the occurrence of the spike detection signal.

Abstract: A voltage regulator having an output terminal provided for being connected to a load, including an amplifier having its inverting input connected to a reference voltage, and its non-inverting input connected to the output terminal, a charge capacitor arranged between the output terminal and a first supply voltage, first and second voltage-controlled switches each arranged to connect a second supply voltage and the output terminal, and a control means adapted to providing a voltage depending on the output voltage of the amplifier, on the one hand, to the gate of the first switch and, on the other hand, when the current flowing through the first switch reaches a predetermined threshold, to the gate of the second switch.

Abstract: The reading timing device has a data-sensing stage, receiving a sensing-latch signal, and an output stage, including an output buffer and enabled at a first switching edge of a synchronization signal. A reading timing stage generates the sensing-latch signal not before a preset time interval from the first switching edge of the synchronization signal. Thereby, reading, in particular data-latching in the data-sensing stage, is temporarily separated from switching of the output buffers. This separation is obtained using the sync signal. Since the output buffers must switch in a preset time from the rising edge of the sync signal, the pulse of the sensing-latch signal is shifted after this time, and more precisely after the falling edge of the sync signal.

Abstract: A testing head having cantilever probes is presented. The testing head, comprises a backing ring and a resin holder attached to the backing ring, as well as a plurality of contact probes held by the resin holder and formed with respective contact tips arranged to mechanically and electrically contact a plurality of contact pads of at least one device to be tested. The holder is formed with at least one suitably shaped outline to allow different probe rows to emerge in a cantilever manner.

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory device that includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different “bit-layers”, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor.